Principal Design Engineer, High-Speed Interconnect Architect

Semiconductor Engineering; United Kingdom; Remote; GBP 90,000 - 120,000; Full time

Job summary

Semiconductor Engineering is seeking an experienced engineer to own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink.

You will translate system and protocol requirements into implementation-ready specifications, interfaces, registers, and synthesizable RTL, while collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to hit

Responsibilities

• Own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink.
• Translate system and protocol requirements into implementation-ready microarchitecture specifications, interfaces, registers, and synthesizable RTL.
• Drive development from concept through RTL creation, subsystem integration, verification support, synthesis preparation, and final delivery.
• Collaborate with architecture, verification, performance, firmware, physical design, and implementation teams to meet targets for functionality, bandwidth, latency, power, area, and timing.
• Analyze traffic patterns, workloads, queue depths, credits, outstanding transactions, and buffer requirements to guide implementation tradeoffs; mentor engineers and lead technical reviews.

Job description

Semiconductor Engineering is seeking an experienced engineer to own the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across multiple silicon products, including PCIe, CXL, and UALink.

You will translate system and protocol requirements into implementation-ready specifications, interfaces, registers, and synthesizable RTL, while collaborating with architecture, verification, performance, firmware, physical design, and implementation teams to hit