Senior Hardware Engineer - RTL, FPGA & AI-Driven Design

ARM; Cambridge; Hybrid; GBP 70,000 - 110,000; Full time

Job summary

ARM is seeking a Staff Hardware Engineer in the United Kingdom to help develop innovative hardware platforms and subsystems. The role covers architectural exploration, RTL design, verification and synthesis, with collaboration across hardware teams to translate requirements into efficient digital hardware.

The position involves performance/power/area trade‑offs, direct involvement with architecture decisions, and exploration of AI‑assisted tooling to improve design workflows and automation.

Qualifications

• Experience designing and verifying synthesizable RTL using SystemVerilog or Verilog.
• Ability to develop and maintain testbenches and investigate functional verification issues.
• Experience using synthesis to evaluate RTL implementation results and support gate‑level builds.
• Ability to analyse technical problems, communicate design decisions clearly and collaborate across engineering disciplines.

Responsibilities

• Design, develop and maintain synthesizable RTL using SystemVerilog or Verilog.
• Translate architectural and functional requirements into efficient hardware implementations.
• Develop verification environments, including testbenches, and perform functional verification.
• Integrate digital IP blocks and subsystems, including interfaces, control logic and datapaths.
• Partner with system architects and engineering teams to evaluate performance, power and area trade‑offs.
• Debug, optimise and integrate RTL, and use synthesis results to assess implementation outcomes.
• Improve hardware development workflows through automation and exploration of AI‑assisted tooling.

Skills

RTL design

SystemVerilog

Verilog

functional verification

synthesis

debugging

communication

Job description

ARM is seeking a Staff Hardware Engineer in the United Kingdom to help develop innovative hardware platforms and subsystems. The role covers architectural exploration, RTL design, verification and synthesis, with collaboration across hardware teams to translate requirements into efficient digital hardware.

The position involves performance/power/area trade‑offs, direct involvement with architecture decisions, and exploration of AI‑assisted tooling to improve design workflows and automation.