Senior Digital ASIC Design Lead - RTL to Tapeout

IC Resources; West Yorkshire; On-site; GBP 90,000 - 125,000; Full time

Job summary

IC Resources is seeking a Senior Digital ASIC Design Engineer to contribute across the RTL and architecture spectrum, from design through tapeout and silicon bring‑up, in a growing semiconductor environment in the UK.

You will collaborate with digital, verification, analogue, physical design and system engineering teams to deliver robust solutions, using SystemVerilog/Verilog and a deep understanding of the ASIC flow.

Qualifications

• Strong digital ASIC/RTL design experience.
• Advanced SystemVerilog or Verilog knowledge.
• Experience through the ASIC flow to tapeout.

Responsibilities

• Develop synthesizable RTL for control logic, data paths and high performance digital blocks.
• Define and integrate digital architectures, including clocks, resets, registers and interfaces.
• Collaborate with verification, analogue, physical design and system engineering teams.

Skills

Digital ASIC design

SystemVerilog/Verilog

ASIC flow to tapeout

RTL integration

Synthesis/Timing/CDC

Cross-functional collaboration

Education

Bachelor's degree in Electronics, Computer Engineering or related field

Job description

IC Resources is seeking a Senior Digital ASIC Design Engineer to contribute across the RTL and architecture spectrum, from design through tapeout and silicon bring‑up, in a growing semiconductor environment in the UK.

You will collaborate with digital, verification, analogue, physical design and system engineering teams to deliver robust solutions, using SystemVerilog/Verilog and a deep understanding of the ASIC flow.