Senior Digital ASIC Design Engineer

IC Resources; Leeds; On-site; GBP 70,000 - 120,000; Full time

Job summary

IC Resources is seeking a Senior Digital ASIC Design Engineer in Leeds to help develop complex ASIC technology from architecture and RTL through to tapeout and silicon bring up.

You will collaborate with digital design, verification, analogue, physical design and system engineering teams to ensure robust designs and first-silicon success.

Qualifications

• Advanced SystemVerilog or Verilog proficiency required.
• Experience delivering ASIC flow to tapeout.
• Strong understanding of synthesis, timing and CDC.
• Experience working with cross-functional engineering teams.
• Degree in Electronics, Computer Engineering or related field.

Responsibilities

• Develop synthesizable RTL for control logic and data paths.
• Define and integrate digital architectures including clocking and interfaces.
• Work with high-speed interfaces (PCIe, AXI/AMBA) and memory/analog interfaces.
• Support RTL sign-off through lint, CDC, RDC and timing analysis.
• Collaborate with verification and physical design teams for robustness.
• Assist FPGA prototyping, tapeout, silicon bring-up and debug.

Skills

SystemVerilog

ASIC tapeout

Synthesis

Timing analysis

CDC analysis

Cross-functional collaboration

Education

Electronics/EE degree

Job description

A growing semiconductor company is expanding its digital design team and is looking for an experienced engineer to work on the development of complex ASIC technology.

This is an opportunity to join a technically ambitious engineering team and contribute across the digital ASIC development flow, from architecture and RTL design through to tapeout and silicon bring up.

As a Senior Digital ASIC Design Engineer, you will work across the design flow from architecture and RTL development through to tapeout and first silicon. You will collaborate closely with teams across digital design, verification, analogue, physical design and system engineering.

The role will involve:

• Developing synthesizable RTL for control logic, data paths, configuration and high performance digital blocks
• Defining and integrating digital architectures, including clocking, resets, registers and block level interfaces
• Working with high speed interfaces and protocols such as PCIe, CXL, UCIe, AXI or AMBA
• Integrating digital logic with memory, analogue and external interfaces
• Supporting RTL sign off through lint, CDC, RDC, synthesis, timing and formal analysis
• Working closely with verification and physical design teams to ensure designs are robust and ready for implementation
• Supporting FPGA prototyping, tapeout, silicon bring up and hardware debug
• Contributing to design reviews and helping solve complex technical challenges across the wider engineering team

Required experience:

• Advanced SystemVerilog or Verilog
• Experience through the ASIC flow to tapeout
• Good understanding of synthesis, timing and CDC
• Experience working with cross functional engineering teams
• Degree in Electronics, Computer Engineering or a related subject

Tel - 01189073075

LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/