Senior Digital ASIC Design Engineer - RTL & Silicon BringUp

IC Resources; Greater London; On-site; GBP 90,000 - 130,000; Full time

Job summary

IC Resources is seeking a Senior Digital Design Engineer for a cutting-edge semiconductor startup delivering advanced ASICs for medical and neurotechnology. The role centers on front-end digital development, architecture, RTL design, verification and supporting silicon bring-up.

You will own digital control interfaces, clocks and calibration with Verilog/SystemVerilog, build verification environments and collaborate closely with analogue engineers for tight integration of mixed-signal blocks.

Qualifications

• Strong experience in digital ASIC design and RTL development.
• Proficient in Verilog or SystemVerilog, with emphasis on low-power mixed-signal ASICs.
• Experience building and maintaining SV testbenches, assertions and coverage.
• Familiarity with lint, CDC/RDC, timing constraints and front-end checks.

Responsibilities

• Own the architecture and RTL development of digital control, communication and power management functionality.
• Develop clean, synthesizable Verilog/SystemVerilog for low power mixed signal ASICs.
• Build and maintain SystemVerilog verification environments with assertions, coverage and self-checking testbenches.
• Collaborate with analogue and system engineers to define interfaces, registers, clocks and calibration functionality.
• Perform linting, CDC/RDC, synthesis and timing analysis; coordinate with Physical Design as needed.
• Support FPGA prototyping, pre-silicon validation and eventual silicon bring-up.

Skills

Verilog/SystemVerilog

Digital ASIC design

RTL development

Digital verification

Job description

IC Resources is seeking a Senior Digital Design Engineer for a cutting-edge semiconductor startup delivering advanced ASICs for medical and neurotechnology. The role centers on front-end digital development, architecture, RTL design, verification and supporting silicon bring-up.

You will own digital control interfaces, clocks and calibration with Verilog/SystemVerilog, build verification environments and collaborate closely with analogue engineers for tight integration of mixed-signal blocks.