Digital ASIC RTL Design Engineer - Low Power SoC

IC Resources; West of England; On-site; GBP 65,000 - 90,000; Full time

Job summary

IC Resources is seeking a Digital ASIC Design Engineer to join an established semiconductor engineering team working on the next generation of low power wireless SoCs.

The role covers the frontend development flow from architecture and RTL development through integration, verification and ultimately silicon. You will own complex digital designs and collaborate with verification, DFT, software and physical implementation teams.

Qualifications

• Experience in ASIC, SoC or digital IC design.
• Hands-on experience with Verilog or SystemVerilog RTL.
• Understanding of the RTL through to synthesis and implementation flow.
• Low power design experience is desirable.

Responsibilities

• Develop RTL for complex digital ICs and SoC designs.
• Collaborate across architecture, design and integration of IP and subsystems.
• Support designs through tape-out and silicon.
• Work with verification, DFT, software and physical implementation teams.
• Contribute to synthesis, timing and design quality activities.
• Work on low power design methodologies and optimize performance and efficiency.
• Use scripting and automation to improve design and development flows.
• Share knowledge across the wider engineering team.

Skills

Verilog/SystemVerilog RTL

ASIC/SoC/digital IC design

RTL design flow

Low power design

Scripting

Design verification

Job description

IC Resources is seeking a Digital ASIC Design Engineer to join an established semiconductor engineering team working on the next generation of low power wireless SoCs.

The role covers the frontend development flow from architecture and RTL development through integration, verification and ultimately silicon. You will own complex digital designs and collaborate with verification, DFT, software and physical implementation teams.