SoC Physical Design Lead – Tape-out Expert

Aion Silicon Ltd; Greater London; On-site; GBP 110,000 - 170,000; Full time

Job summary

Aion Silicon Ltd in Greater London seeks a Principal Engineer – SoC Physical Design to lead ASIC/SoC tape-out and integration from architecture to silicon. You will drive full-chip physical implementation, floorplanning, power/clock distribution, timing closure, and signoff, collaborating with Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

The role requires 15+ years in ASIC/SoC physical design, a track record of multiple tape-outs, and strong leadership

Qualifications

• 15+ years of ASIC/SoC Physical Design experience.
• Proven track record of multiple successful SoC/ASIC tape-outs.
• Strong understanding of ASIC/SoC integration, including floorplanning, clock distribution, power distribution networks, global signal planning, I/O planning, and hard IP integration.
• Experience addressing complex SoC challenges involving multiple voltage domains, multiple clock domains, ESD implementation strategies, mixed-signal integration, and package-aware design considerations.
• Solid knowledge of hierarchical and top-down design methodologies, budgeting techniques, timing convergence, and physical convergence strategies for large-scale SoCs.
• Experience integrating IPs from both internal and external vendors and driving physical implementation requirements throughout the design lifecycle.
• Hands-on experience with large-scale SoCs exceeding >20M gates and operating at frequencies greater than 1GHz.

Responsibilities

• Partner with Front-End and Architecture teams to understand chip architecture and drive physical design considerations early in the development cycle.
• Lead full-chip physical implementation activities including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff.
• Drive physical design methodologies, best-known methods (BKMs), checklists, and implementation guidelines across projects.
• Serve as the technical focal point for physical design execution and coordinate activities across block, subsystem, and top-level implementation teams.
• Define project milestones, track progress, manage dependencies, and drive execution to meet tape-out schedules.
• Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to achieve project goals.
• Drive closure of timing, congestion, power, IR drop, EM, signal integrity, and physical verification requirements.
• Debug and resolve design, flow, and methodology issues, identifying scalable solutions and driving implementation.
• Mentor engineers and contribute to the continuous improvement of design methodologies and automation flows.

Skills

Leadership

Cross-functional collaboration

SoC physical design

Floorplanning

Power integrity

Timing closure

Signoff

Education

B.Tech / M.Tech in Electrical Engineering, Electronics, Computer Engineering, or related discipline

Tools

Calibre

IC Validator (ICV)

Pegasus

RedHawk

Voltus

PrimePower

TCL

Perl

Python

Job description

Aion Silicon Ltd in Greater London seeks a Principal Engineer – SoC Physical Design to lead ASIC/SoC tape-out and integration from architecture to silicon. You will drive full-chip physical implementation, floorplanning, power/clock distribution, timing closure, and signoff, collaborating with Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams.

The role requires 15+ years in ASIC/SoC physical design, a track record of multiple tape-outs, and strong leadership