Senior Digital ASIC Design Engineer

Intellectual Capital Resources Ltd; West of England; On-site; GBP 70,000 - 110,000; Full time

Job summary

Intellectual Capital Resources Ltd is seeking a Senior Digital ASIC Design Engineer to join an established semiconductor engineering team. The role covers front-end development from architecture and RTL through verification to tape-out, offering significant technical ownership of complex digital designs used in high-volume connected products.

Ideal candidates have strong ASIC/SoC experience, hands-on Verilog/SystemVerilog RTL skills, and a deep understanding of the full design flow including

Qualifications

• Strong commercial experience in ASIC, SoC or digital IC design.
• Solid hands on experience with Verilog or SystemVerilog RTL.
• Strong understanding of the digital design flow from RTL through synthesis and implementation.
• Experience taking complex designs through development and integration.
• Good understanding of areas such as synthesis, timing, CDC or low power design.
• Previous experience taking technical ownership of projects or design areas.

Responsibilities

• Leading the development of RTL for complex digital ICs and SoC designs.
• Contributing to architecture and design decisions across IP and larger subsystems.
• Taking ownership of designs through development, integration and tape out.
• Working closely with verification, DFT, software and physical implementation teams.
• Driving synthesis, timing and design quality activities.
• Contributing to low power design methodologies and optimising designs for performance and efficiency.
• Using scripting and automation to improve design and development flows.
• Providing technical guidance and supporting less experienced engineers.

Skills

ASIC/SoC design

RTL design

Digital IC design

Synthesis & timing

Technical ownership

Tools

Verilog

SystemVerilog

Synthesis tools

Job description

This is an exciting opportunity for Senior Digital ASIC Design Engineer to join an established semiconductor engineering team working on the next generation of low power wireless SoCs.

The Senior Digital ASIC Design Engineer will be involved across the front end development flow, from architecture and RTL development through integration, verification and ultimately silicon. The role offers significant technical ownership and the opportunity to contribute to complex digital designs used in high volume connected products.

The role will involve:

• Leading the development of RTL for complex digital ICs and SoC designs
• Contributing to architecture and design decisions across IP and larger subsystems
• Taking ownership of designs through development, integration and tape out
• Working closely with verification, DFT, software and physical implementation teams
• Driving synthesis, timing and design quality activities
• Contributing to low power design methodologies and optimising designs for performance and efficiency
• Using scripting and automation to improve design and development flows
• Providing technical guidance and supporting less experienced engineers

The ideal Senior Digital ASIC Design Engineer will have:

• Strong commercial experience in ASIC, SoC or digital IC design
• Solid hands on experience with Verilog or SystemVerilog RTL
• Strong understanding of the digital design flow from RTL through synthesis and implementation
• Experience taking complex designs through development and integration
• Good understanding of areas such as synthesis, timing, CDC or low power design
• Previous experience taking technical ownership of projects or design areas

This Senior Digital ASIC Design Engineer position would suit an experienced engineer who enjoys staying close to the technical work while taking greater ownership of complex designs and contributing to wider engineering decisions.

For more information, please contact Jordan Browne.