Design Verification Engineer

IC Resources; City of Edinburgh; Hybrid; GBP 60,000 - 90,000; Full time

Benefits offered by this job

Competitive base salary

RSUs and annual bonus

Flexible work options

Job summary

A leading semiconductor company in Edinburgh seeks a Senior Design Verification Engineer to ensure the correctness of complex digital and mixed-signal ASIC designs. The role involves developing verification plans, mentoring engineers, and collaborating with design teams. Candidates should have over 5 years of experience, strong SystemVerilog and UVM skills, and familiarity with ASIC development flows. The position offers competitive salary, RSUs, and flexible work options for UK-based engineers.

Qualifications

• 5+ years’ experience in digital and/or mixed-signal design verification.
• Strong proficiency in SystemVerilog, UVM, and leading simulation tools.
• Solid understanding of RTL design and ASIC development flows.

Responsibilities

• Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs.
• Mentor junior engineers and drive improvements in verification methodologies.
• Collaborate closely with design engineers to interpret specifications.

Skills

SystemVerilog

UVM

Digital design principles

Problem-solving skills

Tools

Synopsys VCS

Cadence Xcelium

Python

Perl

Shell

Job description

Business Manager - Semiconductor Division

Edinburgh

Join a world‑class semiconductor powerhouse and play a key role in cutting‑edge ASIC development.

I am looking for a Senior Design Verification Engineer to join a dynamic hardware development team in Edinburgh. In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed‑signal ASIC designs using advanced verification methodologies.

Key responsibilities

• Develop and execute comprehensive verification plans for complex mixed‑signal ASIC designs
• Create and maintain UVM‑based SystemVerilog testbenches
• Write, debug, and execute test cases to verify functionality, performance, and corner cases
• Perform block‑level and full‑chip verification, including simulation, coverage analysis, and regression management
• Collaborate closely with design engineers to interpret specifications and define verification requirements
• Analyse and resolve issues discovered during verification and post‑silicon validation
• Mentor junior engineers and drive improvements in verification methodologies and infrastructure
• Participate in code reviews and contribute to continuous improvement of design and verification best practices

Qualifications

• 5+ years’ experience in digital and/or mixed‑signal design verification
• Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
• Solid understanding of digital design principles, RTL design, and ASIC development flows
• Experience with scripting languages (Python, Perl, Shell, etc.)
• Familiarity with formal verification, assertion‑based verification, and coverage‑driven verification techniques
• Excellent problem‑solving skills and attention to detail

What’s on offer

• Competitive base salary plus RSUs and annual bonus
• A collaborative, innovative working environment
• Flexible work options – remote work may be considered for UK‑based engineers with full right to work in the UK

• Seniority level: Mid‑Senior level
• Employment type: Full‑time
• Job function: Semiconductor Manufacturing and Computer Hardware Manufacturing