Senior Formal Verification Engineer - Europe

IC Resources; Reading; Hybrid; GBP 50,000 - 70,000; Full time

Job summary

A semiconductor company is seeking a skilled Formal Verification Engineer to support their European design teams. The role involves creating and applying formal verification methodologies for complex digital blocks, collaborating closely with design teams, and improving verification flows. Ideal candidates should have experience in ASIC or FPGA development, proficiency in assertion-based techniques, and scripting skills for automation. The position is full-time and can be based in several locations across Europe.

Qualifications

• Strong background in formal verification for ASIC or FPGA development.
• Experience using formal verification tools, preferable in Cadence ecosystem.
• Proficiency with assertion-based techniques such as SVA or PSL.

Responsibilities

• Create and apply formal verification methodologies for complex digital blocks.
• Review specifications and RTL to build verification plans.
• Develop and maintain formal environments, assertions, and models.
• Collaborate with design teams to analyze results and close issues.
• Support sign-off processes and improve verification flows.

Skills

Formal verification for ASIC or FPGA development

Assertion-based techniques (SVA, PSL)

Formal verification tools usage

Scripting skills (Python, TCL, Perl)

Digital design and CPU/ISA concepts

Clear communication

Tools

Cadence ecosystem

Job description

A semiconductor company is seeking a skilled Formal Verification Engineer to support their European design teams. The role involves creating and applying formal verification methodologies for complex digital blocks, collaborating closely with design teams, and improving verification flows. Ideal candidates should have experience in ASIC or FPGA development, proficiency in assertion-based techniques, and scripting skills for automation. The position is full-time and can be based in several locations across Europe.