Design Verification Engineer

Intellectual Capital Resources Ltd; City of Edinburgh; Hybrid; GBP 60,000 - 90,000; Full time

Benefits offered by this job

RSUs

Development opportunities

Job summary

Intellectual Capital Resources Ltd. is seeking Design Verification Engineers to join a growing semiconductor group in Edinburgh.

You will contribute to digital verification for complete mixed-signal ICs, build advanced verification environments, and help improve methodologies across projects. This role offers a flat culture, strong development opportunities, and a competitive compensation package including RSUs.

Qualifications

• Metric-driven verification: planning, requirements extraction, constrained-random verification.
• Strong SystemVerilog expertise including SVA.
• Testbench development using verification frameworks (e.g. UVM).
• Strong debugging skills; scripting with TCL or Perl.

Responsibilities

• Involved in all aspects of digital verification for complete mixed-signal IC developments.
• Work on sophisticated verification environments and contribute to improving verification methodologies.
• Support and mentor junior engineers; drive improvements in verification methodologies.
• Lead verification activities for larger or more complex projects.

Skills

Verification planning

Requirements extraction

Constrained-random verification

Functional coverage

Code coverage

SystemVerilog

SVA (SystemVerilog Assertions)

Testbench development (UVM)

Debugging

TCL/Perl

CPF/UPF (Power-aware verification)

Formal verification

Tools

UVM

Job description

This is a fantastic opportunity to join a well-established semiconductor company as they continue to grow their multi-disciplinary Verification team. The group has ambitious expansion plans and is seeking Design Verification Engineers to work on complex technical challenges, delivering innovative end-user solutions for leading global consumer brands.

The role

As a Design Verification Engineer, you will be involved in all aspects of digital verification for complete mixed-signal IC developments. You will work on sophisticated verification environments and actively contribute to the ongoing improvement of verification methodologies.

This is an excellent opportunity to become deeply involved in cutting-edge projects within a global organisation. In return, the company offers a strong benefits package, including personal and professional development, a uniquely flat culture, and a competitive compensation package including RSUs.

Career progression

The team is hiring across multiple levels, from Mid-Level through to Staff. More senior engineers will have opportunities to take on additional responsibilities, such as:

• Supporting and mentoring junior engineers
• Driving improvements in verification methodologies
• Leading verification activities for larger or more complex projects

Required skills & experience

Metric-driven verification, including:

• Verification planning
• Requirements extraction
• Directed and constrained-random verification
• Functional and code coverage analysis

• Strong SystemVerilog, including SVA (SystemVerilog Assertions)
• Testbench development using verification frameworks (e.g. UVM)
• Strong debugging skills
• Scripting experience with TCL or Perl
• Power-aware verification using CPF/UPF
• Formal verification and verification qualification techniques (nice to have)

This is a truly superb opportunity to join a growing business based in refurbished, central Edinburgh offices, working on challenging and rewarding technology.

Location: Edinburgh (Newbury can be considered) Working Model: Hybrid (2+ days per week in the office)Relocation & Visa Sponsorship: Available if required