Hybrid Design Verification Engineer (SystemVerilog/UVM)

Intellectual Capital Resources Ltd; City of Edinburgh; Hybrid; GBP 60,000 - 90,000; Full time

Benefits offered by this job

RSUs

Development opportunities

Job summary

Intellectual Capital Resources Ltd. is seeking Design Verification Engineers to join a growing semiconductor group in Edinburgh.

You will contribute to digital verification for complete mixed-signal ICs, build advanced verification environments, and help improve methodologies across projects. This role offers a flat culture, strong development opportunities, and a competitive compensation package including RSUs.

Qualifications

• Metric-driven verification: planning, requirements extraction, constrained-random verification.
• Strong SystemVerilog expertise including SVA.
• Testbench development using verification frameworks (e.g. UVM).
• Strong debugging skills; scripting with TCL or Perl.

Responsibilities

• Involved in all aspects of digital verification for complete mixed-signal IC developments.
• Work on sophisticated verification environments and contribute to improving verification methodologies.
• Support and mentor junior engineers; drive improvements in verification methodologies.
• Lead verification activities for larger or more complex projects.

Skills

Verification planning

Requirements extraction

Constrained-random verification

Functional coverage

Code coverage

SystemVerilog

SVA (SystemVerilog Assertions)

Testbench development (UVM)

Debugging

TCL/Perl

CPF/UPF (Power-aware verification)

Formal verification

Tools

UVM

Job description

Intellectual Capital Resources Ltd. is seeking Design Verification Engineers to join a growing semiconductor group in Edinburgh.

You will contribute to digital verification for complete mixed-signal ICs, build advanced verification environments, and help improve methodologies across projects. This role offers a flat culture, strong development opportunities, and a competitive compensation package including RSUs.