Senior ASIC Verification Architect — Interface IP Lead

Synopsys Inc; Reading; On-site; GBP 50,000 - 75,000; Full time

Benefits offered by this job

Comprehensive health and wellness benefits

Financial benefits

Job summary

Synopsys Inc is seeking an experienced ASIC Digital Verification Engineer to ensure the highest quality of digital designs. The ideal candidate will have extensive experience in ASIC digital verification, particularly with Interface IP protocols like PCIe and DDR. You will design verification environments, create test plans, and mentor junior engineers, all while working within a dynamic and collaborative team. Competitive health benefits and a commitment to continuous innovation are offered in this role based in Reading, UK.

Qualifications

• Extensive experience in ASIC digital verification, especially with Interface IP protocols like PCIe, CXL, DDR.
• Proficiency in System Verilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.

Responsibilities

• Design and optimize verification environments for Interface IP protocols.
• Create and execute test plans for verifying ASIC designs.
• Mentor and guide junior verification engineers.

Skills

ASIC digital verification

Interface IP protocols

System Verilog

UVM methodologies

Analytical skills

Communication skills

Tools

VCS

Model Sim

Job description

Synopsys Inc is seeking an experienced ASIC Digital Verification Engineer to ensure the highest quality of digital designs. The ideal candidate will have extensive experience in ASIC digital verification, particularly with Interface IP protocols like PCIe and DDR. You will design verification environments, create test plans, and mentor junior engineers, all while working within a dynamic and collaborative team. Competitive health benefits and a commitment to continuous innovation are offered in this role based in Reading, UK.