Senior Design Verification Engineer

JR United Kingdom; Coventry; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading company is seeking a Verification Engineer to join their innovative team and contribute to the RISC-V revolution. This role involves developing verification infrastructure, implementing verification strategies, and collaborating with design teams. Competitive salary and excellent benefits are offered in this dynamic environment.

Qualifications

• Strong proficiency in SystemVerilog and UVM with industry experience.
• Understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures preferred.

Responsibilities

• Develop and maintain verification infrastructure alongside design teams.
• Define & implement detailed verification strategies to ensure product quality.
• Manage functional and code coverage metrics for progress tracking.
• Debug and resolve issues while maintaining quality dashboards.

Skills

SystemVerilog

UVM

Verification methodologies

Troubleshooting

Collaboration

Job description

Social network you want to login/join with:

col-narrow-left

Client:

Platform Recruitment

Location:

Coventry, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

col-narrow-right

Job Views:

4

Posted:

31.05.2025

Expiry Date:

15.07.2025

col-wide

Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing ICs with high-impact applications across machine learning, aerospace, and automotive industries.

Enjoy a flat organizational structure with a diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug, and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.