Senior Design Verification Engineer

JR United Kingdom; Birmingham; On-site; GBP 55,000 - 75,000; Full time

Job summary

Join a leading company driving innovations in RISC-V technology as a verification engineer. You'll be responsible for developing verification infrastructure and strategies while collaborating with design teams to ensure product performance across various high-impact applications. This role offers a great chance to develop in a dynamic work environment with excellent benefits.

Qualifications

• Proficiency in SystemVerilog and UVM with experience in verification methodologies.
• Understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.

Responsibilities

• Develop and maintain verification infrastructure with design teams and partners.
• Define and implement verification strategies for product quality.
• Manage coverage metrics and resolve related issues.

Skills

SystemVerilog

UVM

mixed hardware/software verification

Job description

Social network you want to login/join with:

col-narrow-left

Client:

Platform Recruitment

Location:

birmingham, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

col-narrow-right

Job Views:

4

Posted:

31.05.2025

Expiry Date:

15.07.2025

col-wide

Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.