Senior Design Verification Engineer

IC Resources; Cambridge; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

IC Resources is seeking a Staff Verification Engineer in Cambridge to join a stealth-like hardware team building next‑generation quantum computing systems. You will own verification across block, subsystem and multi‑FPGA designs, shaping the verification strategy from the ground up.

Strong hands‑on SystemVerilog and UVM expertise, plus experience in commercial verification planning, are required. Visa sponsorship can be considered for engineers already in the UK.

Qualifications

• Experience with SystemVerilog and UVM for verification across block, subsystem, and multi‑FPGA designs.
• Proven debugging skills across RTL, simulation and hardware.
• Experience owning verification planning and strategy in commercial environments.
• Ability to work in fast‑moving environments with evolving requirements.
• Exposure to software/programming languages such as C, C++, or Python.
• Formal verification experience would be a plus.

Responsibilities

• Lead verification strategy and execution across block, subsystem, and multi-FPGA designs.
• Develop scalable, high-performance UVM environments designed to tackle complex architectures.
• Drive verification with a strong focus on coverage, risk reduction, and system-level behaviour.
• Collaborate closely with the Lead Verification Engineer and cross-functional hardware teams.
• Debug challenging issues spanning RTL, simulation, and hardware platforms.

Skills

SystemVerilog

UVM

Debugging

Verification planning

Python

C/C++

Job description

Cambridge, UK | Full-time | Permanent | Hybrid

The salary range is intentionally broad, reflecting the flexibility to consider engineers at different levels of experience.

Some of the most exciting breakthroughs in computing are happening behind closed doors, and this is your chance to be part of it.

I’m looking for a Staff Verification Engineer to join a stealth-like hardware team in Cambridge working at the forefront of quantum computing and next-generation systems design. This is a rare opportunity to step into a deeply technical, highly collaborative environment where complex hardware challenges meet cutting-edge research.

No quantum computing background is needed. What matters is strong verification expertise, curiosity, and the drive to solve problems that don’t already have answers.

As a Staff Verification Engineer, you’ll take ownership of verification across block, subsystem, and multi-FPGA system-level designs, working alongside some of the brightest engineers in the industry. With visibility across the full hardware stack, you’ll help shape the verification strategy from the ground up and influence the direction of an emerging technology space.

What you’ll be doing

• Lead verification strategy and execution across block, subsystem, and multi-FPGA designs
• Develop scalable, high-performance UVM environments designed to tackle complex architectures
• Drive verification with a strong focus on coverage, risk reduction, and system-level behaviour
• Collaborate closely with the Lead Verification Engineer and cross-functional hardware teams
• Debug challenging issues spanning RTL, simulation, and hardware platforms

What they’re looking for

• Strong hands-on expertise in SystemVerilog and UVM
• Proven debugging skills across RTL, simulation, and hardware
• Experience owning verification planning and strategy in commercial environments
• Comfortable operating in fast-moving environments with evolving requirements
• Exposure to software/programming languages such as C, C++, or Python
• Formal verification experience would be a plus

This is an opportunity to work on technology that very few people in the world are building — inside a team where your ideas, technical depth, and curiosity will genuinely shape what comes next.

Visa sponsorship can be given to those engineers already based in the UK.

For more information contact Rachel Mason at IC Resources.