Senior Design Verification Engineer - CPU / SoC

European Tech Recruit

Cambridge

On-site

GBP 70,000 - 100,000

Full time

8 days ago

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Job summary

European Tech Recruit partners with a UK semiconductor giant to hire a Design Verification Engineer in Cambridge for a permanent, on-site role. The position requires extensive DV experience with CPUs and SoC validation and will involve close collaboration with SOC Architects to validate micro-architectures.

You will develop test and coverage plans, build scalable verification environments, and drive regressions with advanced debugging and metrics.

Qualifications

  • Proven DV experience with CPUs/SoC validation.
  • Ability to develop test and coverage plans for CPU domains.
  • Strong debugging of test failures and regressions.

Responsibilities

  • Work with SOC Architects to validate high-level system requirements and micro-architectural concepts.
  • Develop detailed Test and Coverage plans for specific functional domains within the CPU.
  • Build scalable verification environments, including Stimulus, Checkers, Assertions, and Trackers.
  • Enable features through rigorous regressions and deep-dive debugging of test failures.
  • Report progress using metrics like functional coverage and bug density.

Skills

CPU Verification
SystemVerilog/UVM
Test & Coverage planning
Regression debugging
Collaboration with SOC Architects

Tools

SystemVerilog
UVM
RIS
Formal Verification
Simulators/Waveform viewers
Formal Proof Tools

Job description

We are currently partnered with an industry leading semiconductor giant in the UK looking to expand their team with an experienced Design Verification Engineer to join a high caliber team of engineers working on high-performance CPUs and SoC validation. In this role, you will work closely with Architects to prove the correctness of complex micro-architectures before they reach the hands of millions of global users.

This is a permanent position based in Cambridge - please note this is a full onsite role.

Key responsibilities for this Senior Design Verification Engineer position:
  • Work with SOC Architects to validate high-level system requirements and micro-architectural concepts.
  • Develop detailed Test and Coverage plans for specific functional domains within the CPU.
  • Build scalable and portable verification environments, including Stimulus, Checkers, Assertions, and Trackers.
  • Enable all features under your care through rigorous regressions and deep-dive debugging of test failures.
  • Report progress using advanced metrics, including functional coverage and bug density.
Key requirements:
  • Extensive experience working with CPU technologies with proven skills in domains such as Cache Coherence, Memory Ordering, Branch Prediction, Renaming, and Speculative Execution.
  • Experience with Random Instruction Sequencing (RIS) at the Block and Subsystem levels.
  • In-depth experience with Simulators, Waveform viewers, and Formal Proof Tools.
  • Familiarity with Formal Verification, Assertions, and Silicon bring-up.

Keywords: CPU Verification / Design Verification / DV / SystemVerilog / UVM / Cache Coherence / Branch Prediction / Formal Verification / RIS / SOC / Assembly / Cambridge / Silicon Bring-up

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