Verification / Senior Verification Engineer Cambridge, UK

Riverlane Ltd; Cambridge; On-site; GBP 60,000 - 80,000; Full time

Benefits offered by this job

Annual bonus plan

Private medical insurance

Contributory pension scheme

28 days annual leave

Training and conference budgets

Job summary

A leading quantum computing company in Cambridge is seeking a Verification / Senior Verification Engineer to ensure the quality of high-performance systems. The successful candidate will take ownership of verification plans and design scalable testbenches. Candidates should have commercial experience in verification and familiarity with SystemVerilog. The role includes a comprehensive benefits package and a supportive learning environment, encouraging applications from diverse backgrounds.

Qualifications

• Demonstrable commercial experience in functional verification with ownership of verification planning.
• Proven experience with testbench design using verification frameworks such as UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).

Responsibilities

• Develop and implement scalable testbenches in SystemVerilog.
• Maintain the design verification environment tracking regressions and quality metrics.
• Collaborate with designers to define verification plans based on specifications.

Skills

Functional verification

Testbench design

SystemVerilog assertion

Programming languages (C, C++, Python)

Communication skills

Job description

Cambridge, UK

Cambridge, UK | Full‑time | Permanent | Hybrid

Salary range: broad. Offers will be carefully assessed based on experience, transferable skills, and previous achievements.

Part‑time applications are considered. Please indicate your preferred working schedule in your cover letter.

About us

Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. Without QEC, the industry’s defining technical challenge, these breakthroughs cannot be achieved. Riverlane is the world leader in QEC technology, a complex problem that requires a range of skills, talent, and passion.

Having raised more than $125M in funding to accelerate our cutting‑edge R&D in quantum error correction, Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault‑tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

About the role

We have an exceptional opportunity for a Verification / Senior Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high‑performance, and trusted systems.

In this exciting role you’ll have end‑to‑end visibility across the entire stack, own every aspect of verification, and shape how quality and reliability are built into our cutting‑edge technology. A background in quantum computing is not required—you will learn this along the way.

What you will do

• Proactively work with designers and architects to define verification plans based on design specifications. Take full ownership of detailed test strategies across block‑level and system‑level designs.
• Develop and implement scalable testbenches, including checkers, reference models, and coverage groups in SystemVerilog. Implement self‑testing, directed and random tests to ensure every part of the system performs flawlessly.
• Maintain the health and evolution of the design verification environment, tracking regressions, coverage metrics, and bugs to ensure our systems meet the highest standards of quality and reliability.

What we need

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
• Proven experience with testbench design using verification frameworks such as UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).
• Exposure to different programming languages, such as C, C++, and Python.
• A proactive person who can independently define the scope of work.
• A collaborative person with excellent communication skills, who actively shares (and listens to) constructive feedback.
• Ability to work effectively with ambiguity and changing requirements.
• Experience debugging across RTL, simulation, and hardware.

What you can expect from us

• A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme.
• Equity, so that our team can share in the long‑term success of Riverlane.
• 28 days annual leave, plus bank holidays and enhanced family leave.
• A diverse work environment that brings together experts in many fields—including software and hardware development, quantum information theory, physics, and mathematics—and over 20 different nationalities.
• A learning environment that encourages individual, team, and company growth and development, including a regular programme of learning events, training, and conference budgets.

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

Women and other under‑represented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply—you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.