Graduate Verification Engineer

Riverlane; Cambridge; On-site; GBP 37,000 - 40,000; Full time

Benefits offered by this job

Annual bonus plan

Private medical insurance

Life insurance

Contributory pension scheme

Equity

28 days annual leave

Job summary

Riverlane in Cambridge, UK, is hiring a Graduate Verification Engineer to join our hardware and embedded software teams. You’ll deliver fully verified, high‑performance, trusted systems and gain end‑to‑end visibility across the stack.

You will own verification aspects, learn quantum computing concepts along the way, and contribute to developing robust verification strategies within a growing company.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related discipline.
• Understanding of Digital Logic Design.
• Some familiarity with HDL languages (e.g. Verilog, SystemVerilog) and simulation tools.
• Good communication and problem-solving skills.
• Exposure to scripting languages such as Python.
• Understanding of Object-Oriented Programming.
• Exposure to UVM.

Responsibilities

• Develop verification plans for hardware blocks in Quantum Error Correction Systems.
• Create testbenches using SystemVerilog and UVM.
• Run simulations and debug issues with the design team.
• Collaborate with multi-disciplinary teams to define verification strategies.
• Learn and apply best practices in verification to improve methodologies.

Skills

Digital Logic Design

Communication skills

Problem solving

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Science

Tools

SystemVerilog

HDL (Verilog/SystemVerilog)

UVM

Python scripting

Job description

Cambridge, UK | Full-time | Permanent | Hybrid

Salary: £37,000 - £40,000

About us

Riverlane’smission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved.Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills,talentand passion.

Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality.

We’re making remarkable progress and growing fast.

About the role

We have an exceptional opportunity for a Graduate Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.

In this exciting role you'll have end-to-end visibility across the entire stack, owning different aspects of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.

What you will do - specific responsibilities:

As a Graduate Verification Engineer at Riverlane, you will:

• Help with developing and executing verification plans for hardware blocks in Quantum Error Correction Systems
• Learn and support the creation of testbenches using SystemVerilog and UVM
• Run simulations and perform debugging to resolve issues in collaboration with the design team
• Collaborate with multi-disciplinary teams to understand specifications and define verification strategies for Quantum Error Correction systems
• Learn and apply best practices in verification to make methodology improvements

What we need - Essential Skills/Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related discipline
• Understanding of Digital Logic Design
• Some familiarity with HDL languages (e.g. Verilog, SystemVerilog) and simulation tools
• Good communication and problem-solving skills

Even better if you have…

• Relevant academic projects/internships/work experience
• Exposure to scripting languages such as Python
• Understanding of Object-Oriented Programming
• Exposure to UVM

What can you expect from us

• A comprehensive benefits package that includesan annual bonus plan,private medical insurance, life insurance, and acontributory pension scheme
• Equity, so that our team can share in the long-term success of Riverlane
• 28 days annual leave,plus bank holidays and enhanced family leave
• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory,physicsand maths) and over 20 different nationalities
• A learning environment that encourages individual, team and company growth anddevelopment, including a regular programme of learning events and training and conference budgets

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.

GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details.

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