Design Verification Engineer

IC Resources; Cambridge; On-site; GBP 108,000 - 132,000; Full time

Benefits offered by this job

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Performance-based bonus scheme

Job summary

A tech recruitment firm is seeking a Design Verification Engineer in Cambridge, UK. The role involves creating test plans, writing UVM/SystemVerilog code, and collaborating with teams. Candidates should have over 6 years in verification and a degree in a related field. A competitive salary of up to £120,000 is offered along with share options and bonuses.

Qualifications

• 6+ years of current hands-on experience in block-level/IP-level/SoC-level verification.
• Deep experience with UVM-based testbenches.
• Experience on working with IP's for caches, cache coherency, and memory subsystems is a plus.

Responsibilities

• Create test plans for highly configurable IPs.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.

Skills

Verilog

SystemVerilog

UVM-based testbenches

Knowledge of Arm AMBA protocols

Experience with formal verification techniques

Education

BS, MS in Electrical Engineering, Computer Engineering or Computer Science

Job description

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Business Manager - Semiconductor Division

A US-based start-up has recently expanded into the UK and is building a cutting-edge hardware team comprising ASIC Designers, Verification Engineers, and Architects. With a proven and successful leadership team, this company offers a unique opportunity to be part of the AI revolution from the ground up.

You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play a pivotal part in shaping the company’s technology portfolio—bringing both technical expertise and creative problem-solving to innovative hardware solutions.

Responsibilities :

• Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design teams test plans, failure debug, coverage, etc.

Qualifications and Preferred Skills

• BS, MS in Electrical Engineering, Computer Engineering or Computer Science
• 6+ years and current hands-on experience in block-level/IP-level/SoC-level verification
• Proficiency in Verilog, SystemVerilog
• Deep experience with UVM-based testbenches
• Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
• Understanding of Arm CHI protocol is a plus
• Experience on working with IP's for caches, cache coherency, memory subsystems, interconnects, and NoC's is a plus.
• Experience with formal verification techniques, emulation platforms is a plus

On offer is a competitive base salary of up to £120,000 (dependent on experience), along with share options and a performance-based bonus scheme.

This is a rare opportunity to join the company as one of the first engineers in the UK—and among a select few globally—helping to shape and build a world-class hardware team from the ground up.

To be considered for this role, you must already be living and working in the United Kingdom

Fore more information and a confidential discussion, please contact Rachel Mason at IC Resources.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing and Computer Hardware Manufacturing

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