Senior Verification Engineer

IC Resources; City of Edinburgh; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

RSUs

Annual bonus

Collaborative environment

Job summary

IC Resources in Edinburgh is seeking an experienced verification engineer to ensure the functional correctness of complex digital and mixed-signal ASIC designs. You will develop verification plans, build UVM-based testbenches, and drive coverage and regression across full-chip scenarios.

The role requires 5+ years in digital/mixed-signal verification, strong SystemVerilog/UVM skills, and proficiency with Synopsys VCS or Cadence Xcelium.

Qualifications

• 5+ years of experience in digital and mixed-signal design verification.
• Proficient in SystemVerilog, UVM, and industry-standard verification flows.
• Experience with simulation tools (Synopsys VCS, Cadence Xcelium).
• Scripting skills in Python, Perl, or Shell.
• Strong problem-solving and attention to detail.

Responsibilities

• Develop and execute verification plans for complex mixed-signal ASIC designs.
• Create and maintain UVM-based SystemVerilog testbenches.
• Write, debug, and execute test cases to verify functionality and corner cases.
• Perform block-level and full-chip verification, including simulation and regression management.
• Collaborate with design engineers to define verification requirements.
• Analyse and resolve issues discovered during verification and post-silicon validation.
• Mentor junior engineers and drive improvements in verification methodologies.
• Participate in code reviews and contribute to best practices.

Skills

Digital/mixed-signal verification

SystemVerilog

UVM

Python

Tools

Synopsys VCS

Cadence Xcelium

Python

Perl

Shell

Job description

Join a world-class semiconductor powerhouse in Edinburgh, one of Europe’s most attractive tech hubs. Known for its thriving semiconductor ecosystem, outstanding quality of life, and easy access to nature, Edinburgh offers the perfect balance between cutting-edge engineering work and lifestyle. This role provides an opportunity for experienced verification engineers to make a long-term move to the UK.

In this role, you’ll be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs using advanced verification methodologies.

Key Responsibilities

• Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs
• Create and maintain UVM-based SystemVerilog testbenches
• Write, debug, and execute test cases to verify functionality, performance, and corner cases
• Perform block-level and full-chip verification, including simulation, coverage analysis, and regression management
• Collaborate closely with design engineers to interpret specifications and define verification requirements
• Analyse and resolve issues discovered during verification and post-silicon validation
• Mentor junior engineers and drive improvements in verification methodologies and infrastructure
• Participate in code reviews and contribute to continuous improvement of design and verification best practices

Qualifications

• 5+ years’ experience in digital and/or mixed-signal design verification
• Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS, Cadence Xcelium)
• Solid understanding of digital design principles, RTL design, and ASIC development flows
• Experience with scripting languages (Python, Perl, Shell, etc.)
• Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques
• Excellent problem-solving skills and attention to detail

What’s On Offer

• Competitive base salary plus RSUs and annual bonus
• A collaborative, innovative working environment