Design Verification Engineer

JR United Kingdom; Northampton; On-site; GBP 45,000 - 70,000; Full time

Job summary

A leading company in the technology sector is seeking a Design Verification Engineer in Northampton. The successful candidate will be responsible for verifying CPU connectivity, developing comprehensive test plans, and employing various verification methodologies to ensure high-quality design checks. This position offers an opportunity to work with cutting-edge technology in a dynamic environment.

Qualifications

• Experience with CPU connectivity verification and test methodologies.
• Proficiency in programming languages like C and System Verilog.
• Familiarity with verification techniques and tools including UVM.

Responsibilities

• Verify CPU connectivity to IP blocks using ASMs and GNU toolchain.
• Write test plans and develop test benches.
• Run regressions and debug test failures.

Skills

Verification

Debugging

Test Planning

C Code

UVM

Verilog/System Verilog

Job description

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Design Verification Engineer, northampton

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Client:

ALOIS Solutions

Location:

northampton, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

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Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures and file bug report as needed.

• Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.

• Provide verification report as needed to show all implemented tests passing on the RTL.

• Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases