Senior CPU Engineer

IC Resources

Cambridge

On-site

GBP 85,000 - 130,000

Full time

19 hours ago
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Job summary

IC Resources is seeking a CPU Microarchitecture & RTL Design Engineer for Cambridge, UK. You will define and develop processor microarchitecture, taking concepts from early architectural exploration through detailed specification and RTL implementation.

You will influence architecture and product definition early, collaborating with CPU and chip architects and verification teams throughout the lifecycle.

Qualifications

  • Strong understanding of microprocessor architecture and hands-on experience with CPU design.
  • Experience in RTL development and implementation using Verilog or VHDL.
  • Proficiency with scripting languages such as Python or Perl for tooling and automation.

Responsibilities

  • Explore high-performance CPU strategies with architecture and performance modelling teams.
  • Develop and specify CPU microarchitecture from early exploration to RTL implementation.
  • Own RTL development and refinement to meet power, performance, area and timing targets.
  • Collaborate with Design Verification engineers to support functional verification.
  • Support performance verification and ensure RTL meets defined performance targets.
  • Evaluate architectural trade-offs across performance, power and complexity.

Skills

Microprocessor architecture
RTL design
Verilog/VHDL
Python/Perl scripting
Instruction fetch/decode
Branch prediction
Out-of-order execution
Load/store execution

Tools

Verilog/VHDL tooling

Job description

I am working with a leading global semiconductor technology company looking to expand its CPU engineering team in Cambridge.


This is an opportunity to work on the development of next-generation, high-performance, low-power CPU technology, contributing to products used across advanced computing applications.


As a CPU Microarchitecture & RTL Design Engineer, you will work closely with CPU and chip architects to define and develop processor microarchitecture, taking concepts from early architectural exploration through detailed specification and RTL implementation.


You will be involved throughout the product lifecycle, with the opportunity to influence both architecture and product definition at an early stage.


Responsibilities Will Include


  • Exploring high-performance CPU strategies alongside architecture and performance-modelling teams

  • Developing and specifying CPU microarchitecture, from early architectural exploration and research through to detailed implementation specifications

  • Owning RTL development, assessment and refinement to achieve power, performance, area and timing targets

  • Working closely with Design Verification engineers to support the functional verification strategy

  • Supporting performance verification and ensuring the RTL implementation achieves defined performance targets

  • Evaluating architectural and microarchitectural trade-offs across performance, power and implementation complexity


Experience

I am interested in engineers with a strong understanding of microprocessor architecture and hands‑on experience in one or more of the following areas:



  • Instruction fetch and decode

  • Branch prediction

  • Instruction scheduling and register renaming

  • Out-of-order execution

  • Integer and floating-point execution

  • Load/store execution

  • Prefetching

  • Cache and memory subsystems


You should also have experience with Verilog and/or VHDL, alongside a good understanding of logic design, timing and power implications.


Experience with low-power CPU microarchitecture techniques and high-performance processor design trade-offs would be particularly relevant.


Knowledge of simulation and waveform-debugging tools is expected, alongside experience using scripting languages such as Python or Perl.


Location

Cambridge, UK.


This role offers the opportunity to join a highly experienced CPU engineering team working at the forefront of advanced processor development, with significant involvement across microarchitecture, RTL implementation, performance and verification.


For more information , please contact Rachel Mason.

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