Senior CPU Engineer: Microarchitecture & RTL

IC Resources; Cambridgeshire and Peterborough; On-site; GBP 70,000 - 110,000; Full time

Job summary

IC Resources is partnering with a leading global semiconductor technology company to expand its Cambridge CPU engineering team. The role focuses on next-generation, high-performance, low-power CPU technology, from architectural exploration to RTL implementation and product definition.

As a CPU Microarchitecture & RTL Design Engineer, you will work with CPU architects to define microarchitecture, own RTL development, and contribute across architecture, RTL, verification and power/performance

Qualifications

• Strong understanding of microprocessor architecture.
• Experience with Verilog and/or VHDL.
• Familiar with timing, power and area implications.
• Experience with Python or Perl scripting.
• Knowledge of simulation and waveform-debugging tools.
• Hands-on CPU microarchitecture techniques for high-performance design.

Responsibilities

• Explore high-performance CPU strategies with architecture and performance modelling teams.
• Develop and specify CPU microarchitecture from exploration to RTL implementation.
• Own RTL development and refinement to meet power, performance, area and timing targets.
• Collaborate with Design Verification to support functional verification.
• Support performance verification and ensure RTL meets targets.
• Evaluate architectural trade-offs across performance, power and complexity.

Skills

CPU architecture

RTL design

Verilog/VHDL

Python/Perl

Performance optimization

Simulation/debugging

Job description

IC Resources is partnering with a leading global semiconductor technology company to expand its Cambridge CPU engineering team. The role focuses on next-generation, high-performance, low-power CPU technology, from architectural exploration to RTL implementation and product definition.

As a CPU Microarchitecture & RTL Design Engineer, you will work with CPU architects to define microarchitecture, own RTL development, and contribute across architecture, RTL, verification and power/performance