Senior ASIC Verification Engineer: SystemVerilog/UVM, UPF

Swediumglobal; Greater London; On-site; GBP 90,000 - 120,000; Full time

Job summary

Swedium Global Services is seeking an experienced ASIC Verification Engineer to join our growing verification team. You will lead SystemVerilog/UVM based verification, develop test plans, and verify UPF-powered features for complex ASIC/SoC designs.

Remote from EU position with 8+ years of related experience; strong debugging and collaboration with design teams are essential for timely verification closure and regression testing.

Qualifications

• 8+ years of ASIC/SoC verification experience.
• Strong hands-on experience with SystemVerilog and UVM.
• Good understanding and practical experience with UPF (IEEE 1801).
• Experience in assertion-based verification (SVA) and functional coverage.
• Familiarity with simulators such as Synopsys VCS, Cadence Xcelium or Siemens Questa.
• Strong debugging and analytical skills.

Responsibilities

• Develop and maintain verification environments using SystemVerilog and UVM.
• Perform functional and power-aware verification for complex ASIC/SoC designs.
• Implement and verify UPF-based low-power features, including power domains, isolation, retention, and power state transitions.
• Develop test plans, testcases, assertions, and functional coverage.
• Debug RTL and verification issues in collaboration with design and architecture teams.
• Execute regressions, analyze coverage, and support verification closure.

Skills

SystemVerilog

UVM

UPF

SVA

Functional coverage

Debugging

Education

Bachelor's or Master's in Electronics/Electrical/Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

Swedium Global Services is seeking an experienced ASIC Verification Engineer to join our growing verification team. You will lead SystemVerilog/UVM based verification, develop test plans, and verify UPF-powered features for complex ASIC/SoC designs.

Remote from EU position with 8+ years of related experience; strong debugging and collaboration with design teams are essential for timely verification closure and regression testing.