Senior Digital Verification Engineer for AI ASIC

Olix; West of England; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Equity & Ownership

Proximity Bonus

Retirement Benefits

Job summary

OLIX is seeking Senior / Staff Digital Verification Engineers to own the verification of high-throughput, real-time data-processing silicon across GHz-class clock domains, from algorithm modelling to RTL sign-off and silicon bring-up.

You will collaborate with digital design, optics, and software teams, develop verification environments with SystemVerilog/UVM, constrained-random testing, and formal methods, and contribute to reusable verification methodologies while mentoring junior engineers.

Qualifications

• 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates, continuous streaming data paths, deep pipelining, and robust hand-shaking in advanced CMOS nodes
• Develop and maintain verification environments using SystemVerilog/UVM, including constrained-random testing, coverage closure, and regression automation
• Define and implement assertion-based verification strategies for control logic, data-path correctness, CDC/RDC, and protocol compliance
• Apply formal verification techniques to complement simulation-based verification and accelerate bug discovery
• Model and validate algorithms using MATLAB/Simulink or Python, ensuring functional equivalence from algorithmic models through RTL and gate-level sign-off
• Support FPGA prototyping and silicon bring-up by developing targeted testcases, debug strategies, and post-silicon validation plans
• Collaborate closely with digital design, optical-hardware, mixed-signal, and software teams to ensure correct integration across clock domains, interfaces, and firmware abstractions
• Analyse verification results to identify root causes, drive design fixes, and improve verification efficiency and reuse
• Contribute to verification methodology development, documentation, and design/verification reviews; mentor junior engineers where appropriate

Skills

SystemVerilog

UVM

Assertions (SVA)

CDC/RDC analysis

Formal verification

Python/NumPy

MATLAB/Simulink

GHz-class clock domains

SerDes/PCIe/Ethernet IP verification

Tools

Jasper

Job description

OLIX is seeking Senior / Staff Digital Verification Engineers to own the verification of high-throughput, real-time data-processing silicon across GHz-class clock domains, from algorithm modelling to RTL sign-off and silicon bring-up.

You will collaborate with digital design, optics, and software teams, develop verification environments with SystemVerilog/UVM, constrained-random testing, and formal methods, and contribute to reusable verification methodologies while mentoring junior engineers.