Senior Analog IC Layout Lead - Floorplanning & Tapeout

IC Resources; England; On-site; GBP 60,000 - 90,000; Full time

Job summary

IC Resources is seeking a Senior Layout Engineer for a semiconductor design team based in the Wiltshire area. The role involves taking mixed-signal designs from initial layout through physical verification and tapeout.

You will lead block and chip-level layout, collaborate with analog designers on constraints, and manage physical verification and tapeout activities to ensure successful silicon releases.

Qualifications

• Experience leading block and chip level layout and floorplanning.
• Ability to interface with analog designers on layout topology and constraints.
• Experience managing physical verification and supporting tapeout activities.

Responsibilities

• Leading block and chip level layout and floorplanning.
• Working closely with analog designers on layout topology, constraints and optimisation.
• Managing physical verification and supporting tapeout activities.
• Contributing to successful silicon releases across multiple projects.
• Supporting CAD tools, PDKs and design rule verification.
• Improving layout processes and methodologies.
• Providing technical guidance and mentoring to other engineers.
• Working with internal teams and external suppliers where required.

Skills

Layout engineering

Floorplanning

Mentoring

Analog design collaboration

Tools

CAD tools

PDKs

Design rule verification

Job description

IC Resources is seeking a Senior Layout Engineer for a semiconductor design team based in the Wiltshire area. The role involves taking mixed-signal designs from initial layout through physical verification and tapeout.

You will lead block and chip-level layout, collaborate with analog designers on constraints, and manage physical verification and tapeout activities to ensure successful silicon releases.