Secure SoC/ASIC Design Verification Engineer

ZeroRISC; West of England; On-site; GBP 60,000 - 90,000; Full time

Job summary

zeroRISC in the United Kingdom is seeking a SoC/ASIC Design Verification Engineer to join a security-focused team. You will develop, verify and maintain silicon from architecture to tapeout, and interact with customers to deliver robust, open silicon solutions.

You will build verification environments, write test plans, diagnose issues, and drive coverage closure across power, security and performance. A background in UVM/SystemVerilog or formal verification and a passion for open source are

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science or a related technical field or equivalent experience.
• 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools.
• Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments.

Responsibilities

• Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off.
• Build high quality verification environments at the chip/top and block levels following engineering best practices.
• Write thorough verification documentation including test plans.
• Diagnose, debug, and resolve regression failures and other errors.
• Achieve coverage closure.

Skills

UVM

SystemVerilog

Formal verification

Testbenches

Debugging

Education

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Simulation tools

Verification environments

Job description

zeroRISC in the United Kingdom is seeking a SoC/ASIC Design Verification Engineer to join a security-focused team. You will develop, verify and maintain silicon from architecture to tapeout, and interact with customers to deliver robust, open silicon solutions.

You will build verification environments, write test plans, diagnose issues, and drive coverage closure across power, security and performance. A background in UVM/SystemVerilog or formal verification and a passion for open source are