RISC-V Verification Engineer – UK Design Center

Codasip; Cambridge; On-site; GBP 55,000 - 75,000; Full time

Job summary

Codasip is seeking Verification Engineers to verify RISC-V processors and extensions, develop test benches and verification components, and collaborate with engineers across teams in a fast-paced environment.

You will define verification strategies, run simulations, hunt bugs, and drive root-cause analyses while crafting automated verification flows using SystemVerilog, Python, C++, or Rust on Linux with Git/SVN for automation.

Qualifications

• Commercial experience with functional processor verification methodologies.
• Knowledge of verifying CPU architectures or IP.
• Fluency in SystemVerilog, Python, C++, or Rust.
• Linux familiarity to automate tasks.
• Version control with Git or SVN.

Responsibilities

• Verify RISC-V processors and extensions.
• Develop verification solutions (test benches, stimulus generation, formal environments).
• Collaborate with engineers for end-to-end verification delivery.
• Define verification strategies for blocks and sub-systems.
• Review specifications from a verification perspective.
• Run simulations, hunt bugs, perform root-cause analysis.
• Define, estimate, prioritise and track your own work.
• Craft automated verification flows.

Skills

SystemVerilog

Python

C++

Rust

Linux

RISC-V

Analytical thinking

Team collaboration

Tools

Git

SVN

Job description

Codasip is seeking Verification Engineers to verify RISC-V processors and extensions, develop test benches and verification components, and collaborate with engineers across teams in a fast-paced environment.

You will define verification strategies, run simulations, hunt bugs, and drive root-cause analyses while crafting automated verification flows using SystemVerilog, Python, C++, or Rust on Linux with Git/SVN for automation.