Senior ASIC Verification Engineer — Complex IP/ASIC | Bonus & RSU

IC Resources; Oxford; On-site; GBP 55,000 - 75,000; Full time

Benefits offered by this job

Annual bonus

RSU programme

Life assurance

Challenging projects

Job summary

IC Resources is seeking three Design Verification Engineers to join its UK chip team in Oxford (and Bristol). You will verify complex ASIC and IP designs for automotive, medical, space, and mobile sectors, driving complete verification environments and robust test strategies.

Candidates should have 2+ years in ASIC/IP verification, with strong SystemVerilog/UVM knowledge, testbench development, and exposure to constrained-random methods. UK-based applicants only.

Qualifications

• A 1st or 2:1 degree in Electronics, Physics, Computer Science, or a related discipline from a leading university.
• At least two years' industry experience working on ASIC or IP verification projects.
• Strong knowledge of verification methodologies, particularly SystemVerilog and UVM.
• Experience developing verification infrastructures, testbenches, models, assertions, and functional tests using Verilog and SystemVerilog.
• Familiarity with constrained-random verification methodologies, code coverage analysis, and regression testing.
• Good understanding of VHDL and/or Verilog RTL.
• Solid understanding of modern verification flows and methodologies.

Responsibilities

• Contributing to verification strategies, plans, and methodologies for complex ASIC and IP projects.
• Architecting, developing, and executing complete verification environments and testbenches.
• Developing verification infrastructures, models, assertions, and functional tests.
• Driving verification closure through constrained-random methodologies, coverage analysis, and regression testing.
• Collaborating closely with design teams to ensure first-time-right silicon.
• Actively participating in the wider verification community, helping to introduce new techniques and methodologies to solve customer verification challenges.

Skills

SystemVerilog

UVM

Verilog

VHDL

RTL

Constrained-random

Code coverage

Testbench development

ASIC/IP verification

Education

1st or 2:1 degree in Electronics, Physics, Computer Science, or a related discipline

Job description

IC Resources is seeking three Design Verification Engineers to join its UK chip team in Oxford (and Bristol). You will verify complex ASIC and IP designs for automotive, medical, space, and mobile sectors, driving complete verification environments and robust test strategies.

Candidates should have 2+ years in ASIC/IP verification, with strong SystemVerilog/UVM knowledge, testbench development, and exposure to constrained-random methods. UK-based applicants only.