Senior Design Verification Engineer

IC Resources; Oxford; On-site; GBP 55,000 - 75,000; Full time

Benefits offered by this job

Annual bonus

RSU programme

Life assurance

Challenging projects

Job summary

IC Resources is seeking three Design Verification Engineers to join its UK chip team in Oxford (and Bristol). You will verify complex ASIC and IP designs for automotive, medical, space, and mobile sectors, driving complete verification environments and robust test strategies.

Candidates should have 2+ years in ASIC/IP verification, with strong SystemVerilog/UVM knowledge, testbench development, and exposure to constrained-random methods. UK-based applicants only.

Qualifications

• A 1st or 2:1 degree in Electronics, Physics, Computer Science, or a related discipline from a leading university.
• At least two years' industry experience working on ASIC or IP verification projects.
• Strong knowledge of verification methodologies, particularly SystemVerilog and UVM.
• Experience developing verification infrastructures, testbenches, models, assertions, and functional tests using Verilog and SystemVerilog.
• Familiarity with constrained-random verification methodologies, code coverage analysis, and regression testing.
• Good understanding of VHDL and/or Verilog RTL.
• Solid understanding of modern verification flows and methodologies.

Responsibilities

• Contributing to verification strategies, plans, and methodologies for complex ASIC and IP projects.
• Architecting, developing, and executing complete verification environments and testbenches.
• Developing verification infrastructures, models, assertions, and functional tests.
• Driving verification closure through constrained-random methodologies, coverage analysis, and regression testing.
• Collaborating closely with design teams to ensure first-time-right silicon.
• Actively participating in the wider verification community, helping to introduce new techniques and methodologies to solve customer verification challenges.

Skills

SystemVerilog

UVM

Verilog

VHDL

RTL

Constrained-random

Code coverage

Testbench development

ASIC/IP verification

Education

1st or 2:1 degree in Electronics, Physics, Computer Science, or a related discipline

Job description

This is an excellent opportunity to join a well-established British semiconductor company with a strong reputation built over more than two decades in the industry. Due to continued growth, they are expanding their UK chip team and are looking to hire three Design Verification Engineers to join their teams in either Bristol or Oxford.

As a Design Verification Engineer, you will become part of a highly regarded ASIC team, working on cutting-edge designs for a diverse customer base ranging from innovative start-ups to global blue-chip organisations across the automotive, medical, space, and mobile technology sectors.

With offices across the UK, Europe, India, and South America, the company employs more than 200 people worldwide and continues to invest heavily in its engineering capabilities.

You will play a key role in the verification of complex ASIC and IP designs, working across a variety of challenging projects. You will be expected to quickly understand new designs and verification challenges, contribute to verification planning, and execute robust verification strategies.

Key responsibilities include:

• Contributing to verification strategies, plans, and methodologies for complex ASIC and IP projects
• Architecting, developing, and executing complete verification environments and testbenches
• Developing verification infrastructures, models, assertions, and functional tests
• Driving verification closure through constrained-random methodologies, coverage analysis, and regression testing
• Collaborating closely with design teams to ensure first-time-right silicon
• Actively participating in the wider verification community, helping to introduce new techniques and methodologies to solve customer verification challenges

Requirements

• A 1st or 2:1 degree in Electronics, Physics, Computer Science, or a related discipline from a leading university
• A minimum of two years' industry experience working on ASIC or IP verification projects
• Strong knowledge of verification methodologies, particularly SystemVerilog and UVM
• Experience developing verification infrastructures, testbenches, models, assertions, and functional tests using Verilog and SystemVerilog
• Familiarity with constrained-random verification methodologies, code coverage analysis, and regression testing
• Good understanding of VHDL and/or Verilog RTL
• A solid understanding of modern verification flows and methodologies

In return, you can expect:

• Annual bonus
• Participation in the company's RSU programme following successful completion of probation
• Life assurance
• The opportunity to work on a broad range of technically challenging ASIC projects

This is a fantastic opportunity to play an integral role in the continued growth of a successful British semiconductor company while working on exciting, market-leading technologies.

Please note: Applicants must already be living and working in the United Kingdom and have the right to work in the UK.

Please contact Rachel Mason for more information.