Lead CPU Verification Engineer — Architect of Robust Silicon

Quality Ai; United Kingdom; Remote; GBP 90,000 - 130,000; Full time

Job summary

QualityAI in the United Kingdom is seeking a Senior CPU Design Verification Engineer to advance our custom silicon initiatives. You will build verification components, run constrained-random testing, and drive verification closure across RTL designs.

You will collaborate with design and verification teams on tape-out-ready blocks, apply SystemVerilog/UVM, and leverage formal verification to expose corner cases, contributing to scalable, high-performance processors.

Qualifications

• Bachelor's degree in electrical engineering or equivalent practical experience.
• 8 years of experience with creating and using verification components and environments in standard verification methodology.
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Skills

SystemVerilog

UVM

Constrained-random testing

Formal verification

SVA

RTL verification

ASIC/FPGA verification

Education

Bachelor's degree in Electrical Engineering

Master's degree or PhD in Electrical Engineering

Tools

Formal verification tools

Job description

QualityAI in the United Kingdom is seeking a Senior CPU Design Verification Engineer to advance our custom silicon initiatives. You will build verification components, run constrained-random testing, and drive verification closure across RTL designs.

You will collaborate with design and verification teams on tape-out-ready blocks, apply SystemVerilog/UVM, and leverage formal verification to expose corner cases, contributing to scalable, high-performance processors.