Principal Verification Engineer: Chiplet & MDV Expert

Intellectual Capital Resources Ltd; City of Edinburgh; Sur place; GBP 90 000 - 130 000; Plein temps

Résumé du poste

Intellectual Capital Resources Ltd in Edinburgh is seeking a Principal Verification Engineer to lead verification for advanced Chiplet designs. You will craft verification environments, implement SystemVerilog/UVM scoreboards and self-checking regression suites, and drive MDV-based functional coverage.

The role requires working across ASIC/SoC/IP verification and collaborating with architects and RTL engineers.

Qualifications

• Experience in functional verification using SystemVerilog and UVM.
• Proven MDV experience including functional coverage and verification planning.
• Experience with Formal Verification methodologies and SystemVerilog Assertions.
• Experience developing verification environments for complex ASIC/SoC/IP designs.

Responsabilités

• Develop verification and emulation environments for Chiplet designs.
• Design and implement SystemVerilog/UVM scoreboards and self-checking regression environments.
• Develop functional coverage models and contribute to MDV methodologies.
• Create SystemVerilog Assertions for Formal Verification and simulation.
• Develop and integrate hardware emulation environments.
• Integrate Verification IP (VIP) into simulation and emulation environments.
• Define and manage verification plans for comprehensive coverage and closure.
• Collaborate with architects and RTL designers to tackle verification challenges.
• Participate in design reviews and contribute to verification best practices.

Connaissances

SystemVerilog

UVM

MDV

Formal Verification

Verification planning

SystemVerilog Assertions

Formation

Degree in Electrical/Electronic Engineering, Microelectronics or related

Description du poste

Intellectual Capital Resources Ltd in Edinburgh is seeking a Principal Verification Engineer to lead verification for advanced Chiplet designs. You will craft verification environments, implement SystemVerilog/UVM scoreboards and self-checking regression suites, and drive MDV-based functional coverage.

The role requires working across ASIC/SoC/IP verification and collaborating with architects and RTL engineers.