GPU Verification Lead - RTL/UVM Expert

IC Resources; West of England; On-site; GBP 60,000 - 90,000; Full time

Job summary

IC Resources is seeking a GPU Verification Engineer for their graphics-focused GPU division in the United Kingdom. The role involves delivering verification for GPU components, creating UVM testbenches, and participating in design and verification reviews.

You will work on cutting-edge graphics, AI, and connectivity IP; you may mentor others and help define verification strategies for complex RTL designs. A strong background in SystemVerilog/UVM is required.

Qualifications

• Have a proven track record of developing verification environments for complex RTL designs.
• Excellent understanding of constrained-random verification methodology and challenges of verification closure.
• Confident in defining verification requirements and deriving testbench implementation details.
• Able to perform root-cause analysis of complex issues and resolve them promptly.
• Strong knowledge of SystemVerilog and UVM.

Responsibilities

• Deliver all verification activities for a GPU component or sub-system from planning to sign-off.
• Create verification plans and maintain UVM testbench components.
• Participate in design specification reviews from verification perspective.
• Develop testbenches, tests, sequences, and coverage plans.
• Estimate effort and track your own work.
• Influence and advance GPU verification methodology.
• Lead, coach and mentor team members.
• Contribute to design and verification reviews and suggest improvements.

Skills

RTL verification

Root-cause analysis

Leadership/mentoring

Tools

SystemVerilog

UVM

Constrained-random verification

Job description

IC Resources is seeking a GPU Verification Engineer for their graphics-focused GPU division in the United Kingdom. The role involves delivering verification for GPU components, creating UVM testbenches, and participating in design and verification reviews.

You will work on cutting-edge graphics, AI, and connectivity IP; you may mentor others and help define verification strategies for complex RTL designs. A strong background in SystemVerilog/UVM is required.