Senior Digital Verification Architect for Chiplets

Cadence; City of Edinburgh; On-site; GBP 90,000 - 120,000; Full time

Job summary

Cadence in Edinburgh seeks a Digital Electronics Principal Verification Engineer to lead verification activities for complex Chiplet designs. You will craft verification and emulation environments, develop UVM-based scoreboards, and implement MDV approaches within ISO-9001 aligned processes, collaborating with architects and design teams.

Based in Edinburgh, you will work with Cadence SSG to deliver advanced IP solutions and drive high-quality verification across platforms and tools, including

Qualifications

• Degree in Electrical/Electronic Engineering or related discipline
• 10+ years' experience in microelectronics/EDA industry
• Experience of Verilog RTL Design essential
• Experience of Metric Driven Verification essential
• Experience of Formal Verification Methodologies essential
• Excellent oral and written English essential
• Self-motivated with planning and communication skills

Responsibilities

• Develop Verification and Emulation Environments for complex Chiplet Designs
• Develop UVM-SV Scoreboards for self-checking regressions
• Develop Functional Coverage as part of Metric Driven Verification Environments
• Develop SystemVerilog Assertions for use in Formal and Simulation Environments
• Develop Emulation Environments based on Cadences Palladium Emulator Product
• Integrate Cadence Verification IP (VIP) for Simulation Environments
• Integrate Accelerated VIP (AVIP) for Emulation Environments
• Define and Manage Verification Plans (vPlans) using Cadence vManager tools
• Create and Management of Automated Regression Environments, e.g. Jenkins, GIT
• Participate in Technical Review Meetings and ISO-9001 Checklist Reviews
• Collaborate with Architects and Design Engineers to debug complex test scenarios

Skills

Verilog RTL Design

Metric Driven Verification

Formal Verification

SystemVerilog

UVM

English communication

Planning & coordination

Education

Electrical/Electronic Engineering degree

Tools

Cadence Palladium

Git

Jenkins

vManager

Job description

Cadence in Edinburgh seeks a Digital Electronics Principal Verification Engineer to lead verification activities for complex Chiplet designs. You will craft verification and emulation environments, develop UVM-based scoreboards, and implement MDV approaches within ISO-9001 aligned processes, collaborating with architects and design teams.

Based in Edinburgh, you will work with Cadence SSG to deliver advanced IP solutions and drive high-quality verification across platforms and tools, including