Principal Digital RTL Engineer — SoC & Silicon Impact

Cadence Design Systems; City of Edinburgh; Hybride; GBP 90 000 - 150 000; Plein temps

Avantages offerts par ce poste

Travel <10%

Résumé du poste

Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs within the PSG. You will own RTL from architectural concepts through synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems.

The role targets senior engineers with expertise in SystemVerilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of RTL/ASIC design experience.
• Proficiency in Verilog or SystemVerilog.
• Experience developing synthesizable RTL for ASIC/FPGA implementations.
• Familiarity with simulation and RTL debugging.
• Understanding of common SoC interfaces and protocols.
• Knowledge of synthesis, timing, and physical implementation considerations.
• Strong written and verbal communication skills.
• Ability to work in a multidisciplinary engineering team and communicate with customers.

Responsabilités

• Design, implement, and integrate high-quality synthesizable RTL using SystemVerilog.
• Translate architectural specs into robust microarchitectures and RTL implementations.
• Collaborate with architects and senior engineers on requirements.
• Develop RTL that meets performance, power, and area constraints.
• Participate in RTL design reviews and improve design methodologies.
• Create and maintain test environments with verification engineers.
• Debug functional issues using simulation and debugging tools.
• Coordinate with verification and physical design teams during issues resolution.
• Document design decisions, interfaces, and implementation details.

Connaissances

Verilog/SystemVerilog

Digital logic design

RTL debugging

SoC interfaces

Synthesis & timing

Problem solving

Communication skills

Cross-functional collaboration

Formation

Electrical/Computer Engineering degree

Description du poste

Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs within the PSG. You will own RTL from architectural concepts through synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems.

The role targets senior engineers with expertise in SystemVerilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions