Hardware Engineer Intern: FPGA/ASIC with OCaml & Hardcaml

TU Berlin; Greater London; On-site; GBP 18,000 - 24,000; Full time

Job summary

Jane Street offers an internship where you will work closely with full-time engineers on real hardware design projects. You will apply programming language techniques to improve RTL design and testing using Hardcaml, OCaml, and related tools.

The program pairs interns with mentors, providing hands-on learning and exposure to our internal systems. You will contribute to FPGA or ASIC related tasks, gaining practical experience while exploring hardware design in a dynamic environment.

Qualifications

• Comfortable with a software programming language.
• Experienced with a Hardware Description language (VHDL, Verilog, Chisel, Pymtl, or other).
• Experienced with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs.
• Experienced with building a working hardware project (either FPGA or ASIC).
• Interested in learning how to use FPGAs or ASICs in networking context.

Responsibilities

• Work on hardware design projects mentored by full-time colleagues.
• Gain exposure to the Hardcaml tech stack used for RTL design and testing.
• Contribute to shaping projects from concept to a working design.

Skills

Programming language

HDL experience

FPGA/ASIC tools

Project experience

English fluency

Tools

Vivado

Quartus

Genus

Innovus

Job description

Jane Street offers an internship where you will work closely with full-time engineers on real hardware design projects. You will apply programming language techniques to improve RTL design and testing using Hardcaml, OCaml, and related tools.

The program pairs interns with mentors, providing hands-on learning and exposure to our internal systems. You will contribute to FPGA or ASIC related tasks, gaining practical experience while exploring hardware design in a dynamic environment.