Hardware Engineer (FPGA/ASIC) Internship, June-September

Amsterdam Quant Society; Greater London; Hybrid; GBP 13,000 - 20,000; Full time

Job summary

Jane Street seeks a Hardware Engineer Internship (FPGA/ASIC) in London to design and test hardware systems from concept to RTL, testing, and integration. You will work with OCaml and Hardcaml in the same environment used by full-time engineers, gaining exposure to the firm’s hardware stack.

Prior knowledge of Hardcaml or OCaml is not required, and the project may focus on FPGA or ASIC platforms, depending on background.

Qualifications

• Experience with HDL or hardware construction languages.
• At least one FPGA/ASIC project from coursework, professional work, or personal project.
• Comfort programming in at least one software language.
• Experience using FPGA/ASIC vendor tools such as Vivado or Quartus.
• Interest in how programmable hardware is used in networking.

Responsibilities

• Design and test FPGA or ASIC systems from concept through RTL, testing, integration, and working design.
• Work with OCaml and Hardcaml for RTL design, testing, and integration.
• Collaborate within Jane Street's hardware/software environment.

Skills

Programming experience

HDL languages

FPGA/ASIC tools

FPGA/ASIC project

Networking hardware interest

Tools

Hardcaml

OCaml

Vivado

Quartus

Genus

Innovus

Job description

Hardware Engineer (FPGA/ASIC) Internship, June-September

Design and test FPGA or ASIC systems using OCaml and Hardcaml, taking a hardware application from concept through RTL, testing, integration, and working design.

This internship combines hardware engineering with programming-language technology. Jane Street uses Hardcaml, an OCaml library for describing hardware in RTL, and interns work inside the same development environment used by its full-time hardware engineers.

What you will work on

The hardware team works on both FPGA and ASIC designs. Your project is chosen according to your background and is intended to give you exposure to Jane Street’s shared Hardcaml stack while targeting either an FPGA or ASIC platform. Interns are expected to take a hardware application from concept toward a working design, with most project work involving OCaml and Hardcaml for RTL design, testing, and integration.

Hardcaml is closely integrated with Jane Street’s internal software-development tools, so the internship also gives exposure to the libraries and infrastructure that support the firm’s broader engineering environment. Prior knowledge of Hardcaml or OCaml is not required.

What Jane Street expects

• Comfort programming in at least one software language.
• Experience with a hardware description or construction language such as VHDL, Verilog, Chisel, or PyMTL.
• Experience using FPGA or ASIC vendor tools such as Vivado, Quartus, Genus, or Innovus.
• At least one working FPGA or ASIC project from coursework, professional work, or a personal project.
• Interest in how programmable hardware is used in networking.

No finance, OCaml, or functional-programming background is required.

Details

Role information

Location London, United Kingdom

Job type Internship

Category Software Engineering

Company

New York, United States

Global quantitative trading and technology firm known for mathematical problem-solving, market making, and collaborative research-driven trading.