FPGA/ASIC Hardware Intern – OCaml & Hardcaml

Amsterdam Quant Society; Greater London; Hybrid; GBP 13,000 - 20,000; Full time

Job summary

Jane Street seeks a Hardware Engineer Internship (FPGA/ASIC) in London to design and test hardware systems from concept to RTL, testing, and integration. You will work with OCaml and Hardcaml in the same environment used by full-time engineers, gaining exposure to the firm’s hardware stack.

Prior knowledge of Hardcaml or OCaml is not required, and the project may focus on FPGA or ASIC platforms, depending on background.

Qualifications

• Experience with HDL or hardware construction languages.
• At least one FPGA/ASIC project from coursework, professional work, or personal project.
• Comfort programming in at least one software language.
• Experience using FPGA/ASIC vendor tools such as Vivado or Quartus.
• Interest in how programmable hardware is used in networking.

Responsibilities

• Design and test FPGA or ASIC systems from concept through RTL, testing, integration, and working design.
• Work with OCaml and Hardcaml for RTL design, testing, and integration.
• Collaborate within Jane Street's hardware/software environment.

Skills

Programming experience

HDL languages

FPGA/ASIC tools

FPGA/ASIC project

Networking hardware interest

Tools

Hardcaml

OCaml

Vivado

Quartus

Genus

Innovus

Job description

Jane Street seeks a Hardware Engineer Internship (FPGA/ASIC) in London to design and test hardware systems from concept to RTL, testing, and integration. You will work with OCaml and Hardcaml in the same environment used by full-time engineers, gaining exposure to the firm’s hardware stack.

Prior knowledge of Hardcaml or OCaml is not required, and the project may focus on FPGA or ASIC platforms, depending on background.