Design Verification Engineer

JR United Kingdom; Southampton; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading company in the technology sector is seeking a Design Verification Engineer in Southampton. The role involves verifying CPU connectivity to IP blocks, executing regression tests, and developing comprehensive test plans and methodologies. Candidates should be proficient in C, SystemVerilog, and various verification techniques, with the responsibility of providing detailed verification reports.

Qualifications

• Experience with CPU connectivity verification and SoC/Subsystems.
• Proficiency in C, SystemVerilog, and UVM.
• Ability to write test plans and develop test benches.

Responsibilities

• Verify CPU connectivity to IP blocks and run regressions.
• Develop tests to meet functional and code coverage requirements.
• Provide verification reports on implemented tests passing.

Skills

Verification techniques

Debugging

Test methodologies

C programming

SystemVerilog

Verilog

UVM

Functional verification

Education

Bachelor's degree in Engineering or related field

Tools

GNU toolchain

Simulators and emulators

Job description

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Design Verification Engineer, Southampton

Client: ALOIS Solutions

Location: Southampton, United Kingdom

Job Category: Other

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EU work permit required: Yes

Job Views: 1

Posted: 31.05.2025

Expiry Date: 15.07.2025

Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
• Write test plans, define test methodologies, develop test benches, write test cases, complete functional verification, and close coverage for all the design blocks in the SoCs/Subsystems.
• Run regressions, debug test failures, and file bug reports as needed.
• Develop tests to meet functional and code coverage requirements based on analysis of coverage gaps.
• Provide verification reports showing all implemented tests passing on the RTL.
• Utilize methodologies including design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases.