Senior Design Verification Engineer

JR United Kingdom; Southampton; On-site; GBP 45,000 - 70,000; Full time

Job summary

A leading company in the RISC-V revolution seeks a Senior Design Verification Engineer in Southampton. The role involves developing verification strategies, collaborating with design teams, and ensuring product quality through innovative verification infrastructure. Ideal candidates will possess strong skills in SystemVerilog and UVM, with a preference for RISC-V experience.

Qualifications

• Strong proficiency in SystemVerilog and UVM.
• Experience with mixed hardware/software verification.
• Preferred experience with RISC-V architectures.

Responsibilities

• Develop and maintain verification infrastructure.
• Define and implement verification strategies.
• Manage functional and code coverage metrics.
• Troubleshoot and resolve issues with quality tracking.

Skills

SystemVerilog

UVM

Mixed hardware/software verification

RISC-V architecture

Job description

Social network you want to login/join with:

Senior Design Verification Engineer, southampton

col-narrow-left

Client:

Platform Recruitment

Location:

southampton, United Kingdom

Job Category:

Other

-

EU work permit required:

Yes

col-narrow-right

Job Views:

4

Posted:

31.05.2025

Expiry Date:

15.07.2025

col-wide

Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.