Design Verification Engineer

JR United Kingdom; Swindon; On-site; GBP 40,000 - 60,000; Full time

Job summary

A leading technology firm in Swindon is looking for a Design Verification Engineer to ensure CPU connectivity and enhance design verification processes. This role involves working with advanced methodologies and toolchains, focusing on functional and code coverage across various test cases. Candidates should be proficient in C, SystemVerilog, and UVM, and have strong debugging skills. Joining this esteemed company provides an excellent opportunity to contribute to cutting-edge technology projects.

Qualifications

• Experience in verification methodologies and techniques.
• Proficiency in C, SystemVerilog, and UVM.
• Ability to write test plans and execute functional verification.

Responsibilities

• Verify CPU connectivity using ASM boot and C code.
• Develop test benches, write test cases, and ensure functional coverage.
• Run regressions and debug failures, providing verification reports.

Skills

Verification Techniques

Debugging

C/C++

SystemVerilog

UVM

Tools

GNU Toolchain

Verilog

Simulators and Emulators

Job description

Design Verification Engineer, Swindon, Wiltshire

Client:

ALOIS Solutions

Location:

Swindon, Wiltshire, United Kingdom

Job Category:

Other

EU work permit required:

Yes

Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

Job Description:

• Verify CPU connectivity to IP blocks using ASM boot, C code, and GNU toolchain.
• Write test plans, define test methodologies, develop test benches, write test cases, and complete functional verification and coverage closure for all design blocks in the SoCs/Subsystems.
• Run regressions, debug test failures, and file bug reports as needed.
• Develop tests to meet functional and code coverage requirements based on coverage analysis.
• Provide verification reports to demonstrate all tests passing on the RTL.
• Utilize methodologies including design checks, verification techniques with simulators and emulators such as UVM, formal, Verilog/SystemVerilog testbenches, and C, SystemVerilog, UVM test cases.