Design Verification Engineer

JR United Kingdom; Bath; On-site; GBP 40,000 - 65,000; Full time

Job summary

A global Semiconductor giant is seeking a skilled Design Verification Engineer to join their team in Bristol. The successful candidate will be responsible for verifying complex digital designs, ensuring functionality meets specifications, and collaborating across teams to enhance verification processes and methodologies.

Qualifications

• Mid-Senior level position.
• Solid understanding and hands-on experience with UVM and SystemVerilog required.
• Proficiency in scripting languages such as Perl, Python, or TCL is necessary.

Responsibilities

• Developing and implementing verification plans for digital designs using UVM.
• Writing and maintaining verification test benches, test cases, and coverage models.
• Performing functional and code coverage analysis.

Skills

UVM

SystemVerilog

Perl

Python

TCL

Education

Bachelor's or Master's degree in Electrical Engineering

Bachelor's or Master's degree in Computer Engineering

Bachelor's or Master's degree in a related field

Job description

Social network you want to login/join with:

I am looking for a skilled Design Verification Engineer to join a dynamic team at a global Semiconductor giant in Bristol. The Design Verification Engineer will be responsible for verifying complex digital designs and ensuring that the functionality and performance meet the required specifications.

Responsibilities

• Developing and implementing verification plans for digital designs using UVM (Universal Verification Methodology)
• Collaborating with cross-functional teams to understand design requirements and contributing to the design verification strategy
• Writing and maintaining verification test benches, test cases, and coverage models
• Performing functional and code coverage analysis to ensure comprehensive verification of the design
• Debugging test failures and working closely with design teams to resolve issues
• Contributing to the improvement of verification processes and methodologies

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Solid understanding and hands-on experience with UVM and SystemVerilog
• Proficiency in scripting languages such as Perl, Python, or TCL
• Mid-Senior level

As a Design Verification Engineer, the individual will spend their days collaborating with design and verification teams to ensure successful verification and validation of digital designs. They will write and maintain test cases, analyze code coverage, and participate in debugging and issue resolution activities. The role will also involve contributing to the improvement of verification processes and methodologies and engaging in cross-functional communication to align on design verification strategies.

For more information, please contact Rachel Mason at IC Resources.