Senior Design Verification Engineer

JR United Kingdom; Portsmouth; On-site; GBP 45,000 - 70,000; Full time

Job summary

Join a rapidly expanding company leading the RISC-V revolution as a Senior Design Verification Engineer in Portsmouth. You'll develop verification infrastructures, work closely with design teams, and implement strategies to ensure product quality. If you're proficient in SystemVerilog and UVM, this role offers a diverse workload and excellent benefits.

Qualifications

• Strong proficiency in SystemVerilog and UVM.
• Substantial experience in industry-standard verification methodologies.
• Solid understanding of mixed hardware/software verification approaches.

Responsibilities

• Develop and maintain verification infrastructure in collaboration with design teams.
• Define and implement verification strategies to ensure product quality.
• Manage functional and code coverage metrics.

Skills

SystemVerilog

UVM

Verification Methodologies

Mixed Hardware/Software Verification

Job description

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Senior Design Verification Engineer, portsmouth, hampshire

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Client:

Platform Recruitment

Location:

portsmouth, hampshire, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

4

Posted:

31.05.2025

Expiry Date:

15.07.2025

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Job Description:

Join an innovative, rapidly expanding company at the forefront of the RISC-V revolution developing IC that has high-impact applications across machine learning, aerospace and automotive.

Flat structure with a highly diverse workload and excellent benefits.

Responsibilities:

• Develop and maintain verification infrastructure in collaboration with design teams and external partners.
• Define and implement detailed verification strategies and architectures to ensure product quality and performance.
• Manage functional and code coverage metrics to track and report progress.
• Troubleshoot, debug and resolve issues while maintaining quality tracking dashboards and automated regression tests.

Requirements:

• Strong proficiency in SystemVerilog and UVM, with substantial experience in industry-standard verification methodologies.
• A solid understanding of mixed hardware/software verification approaches.
• Experience with RISC-V architectures is preferred.
• Proven ability to work effectively with design teams and external partners to achieve project goals.