Design Verification Engineer

JR United Kingdom; Bournemouth; On-site; GBP 40,000 - 70,000; Full time

Job summary

A leading company in the verification sector seeks a Verification Engineer to enhance CPU connectivity and develop comprehensive test plans. The ideal candidate will have experience with UVM, Verilog, and SystemVerilog methodologies, ensuring high standards in functional verification for complex SoCs. Applicants should be adept at running regressions and understanding coverage requirements to drive quality results.

Qualifications

• Experience with verification methodologies and test plan development.
• Proficiency in programming languages like C, SystemVerilog.
• Ability to debug test failures and file bug reports.

Responsibilities

• Verify CPU connectivity using ASM boot and C code.
• Develop tests to meet functional and code coverage requirements.
• Provide verification reports demonstrating all tests passing.

Skills

CPU connectivity

Conventional verification techniques

Debugging

Tools

GNU toolchain

UVM

Verilog

SystemVerilog

Job description

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Client:

ALOIS Solutions

Location:

Bournemouth, United Kingdom

Job Category:

Other

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EU work permit required:

Yes

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Job Views:

1

Posted:

31.05.2025

Expiry Date:

15.07.2025

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Job Description:

• Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)

• Tasks include writing test plans, defining test methodologies, developing test benches, writing test cases, completing functional verification, and closing coverage for all the agreed design blocks in the SoCs/Subsystems

• Run regressions, debug test failures, and file bug reports as needed.

• Develop tests to meet functional coverage and code coverage requirements based on analysis of coverage gaps.

• Provide verification reports to demonstrate all tests passing on RTL.

• Methodologies include design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/SystemVerilog based testbenches, and C, SystemVerilog, UVM based test cases.