Verification Engineer (W/M)

Dolphin Design SAS; Meylan; Sur place; EUR 70 000 - 100 000; Plein temps

Résumé du poste

Dolphin Design SAS, based in Meylan, France, is seeking an IP Verification Engineer to join the verification team. The role focuses on functional verification of power management IPs and involves UVM testbenches, protocol checks, and coverage strategies.

You will contribute to ISO 26262 safety verification campaigns, fault injection, and formal verification while growing your expertise across UVM, SystemVerilog, and EDA tools in a dynamic hardware environment.

Qualifications

• Requires a strong UVM-based verification background.
• Solid SystemVerilog (classes, constraints, interfaces) and RTL understanding.
• Experience with functional/coverage-driven verification and SVA assertions is essential.
• Familiarity with ISO 26262 functional safety aspects is advantageous.

Responsabilités

• Develop and maintain verification plans from specifications.
• Build and debug UVM environments with agents, sequences, scoreboards.
• Create reusable, parameterized SystemVerilog testbenches across IPs.
• Write constrained-random stimuli and checks; develop protocol coverage.
• Support fault injection, safety verification, and formal verification activities.
• Collaborate with seniors, leads, and designers to drive verification closure.

Connaissances

UVM

SystemVerilog

SVA assertions

RTL

Code coverage

Scripting

Linux/Windows

EDA tools

Formation

Engineering degree or Master's degree (Bac+5)

Outils

Cadence

Siemens EDA

Synopsys

Questa Formal

JasperGold

Description du poste

To support the growth of our Power Management business and meet our customers' needs around density, power consumption, and operating frequency for their integrated circuits, we are looking for an IP Verification Engineer (W/M), based in Meylan, France.

As part of our verification team, you will work 100% on functional verification of products designed to optimize the energy efficiency of our customers' circuits, across fields such as Edge-IoT, automotive, and high-performance computing (HPC).

Working closely with senior verification engineers, tech leads, and designers, you will help build effective verification strategies that cut down validation time while maximizing coverage, in order to hit the performance and power targets of products such as the Maestro Power Manager Unit (PMU) and the Meerkat distributed margin sensor.

For IPs aimed at the automotive market, you will help verify ISO 26262 requirements and assess how robust blocks are against permanent and transient faults. This role will let you gradually grow your scope - from UVM simulation into fault injection and formal verification.

Your missions

Functional verification (UVM)

• Help define the verification plan (coverage-driven methodology) from product specifications, and track it through to closure on your scope

• Build and debug UVM verification environments: agents, sequences, virtual sequencer, scoreboards, reference models, RAL (uvm_reg), factory, callbacks, hierarchical configuration

• Build reusable, parameterized testbenches (SystemVerilog) that are portable across different IP configurations

• Write directed and constrained-random stimuli, making use of constrained randomization

• Build checkers and SVA assertions, along with the bind strategy behind them

• Debug gaps between spec and RTL, and support the design team on your scope

• Integrate and configure protocol VIPs, or build UVM agents yourself when the IP calls for it

• Build protocol compliance checkers, end-to-end scoreboards, and dedicated protocol coverage (transactions, back-to-back cases, edge cases, error handling, arbitration)

Functional safety and fault injection (ISO 26262)

• Help verify safety requirements and justify the hardware metrics (SPFM, LFM, PMHF)

• Build and run fault injection campaigns (stuck-at for permanent faults, SEU/SET for transient faults): instrument the testbench, select and propagate faults, define detectors and observables

• Analyze fault campaign results, help classify faults (detected, undetected, safe, residual), and feed that into the FMEDA analysis

• Flag improvement opportunities on safety mechanisms back to the design team

• Build up your skills on fault simulation and formal safety verification (FSV) tools, to cut down the effort needed to qualify unclassified faults

Couverture

• Implement the functional coverage strategy: covergroups, coverpoints, crosses, bins, and transitions derived from the verification plan, including for parameterized IPs

• Analyze code coverage (line, branch, condition, expression, toggle, FSM)

• Investigate coverage gaps, justify and document exclusions, and log waivers in the refinement files with supporting justification

• Use coverage and regression management tools, and help drive coverage closure to sign-off criteria

Formal verification

• Write SVA properties and environment constraints (assumes), and build strategies to reach convergence

• Run the relevant formal apps: property checking (FPV), connectivity check, register map check, X-propagation, deadlock detection, feasibility analysis to justify coverage waivers

• Analyze and debug counterexamples, and assess formal completeness (proof core, formal coverage)

• Work with Questa Formal and JasperGold

Methodology and project execution

• Keep up with the latest verification techniques, tools, and technologies

• Help continuously improve and maintain the verification methodology and flow

• Contribute to workload estimates and progress tracking on your activities

• Work closely with tech leads, project managers, designers, and other team members

You're about to become a Dolphin...

You have an engineering degree or a Master's degree (Bac+5) and at least 5 years of experience in functional verification of digital circuits.

You're technically curious, rigorous in how you analyze problems, and you enjoy digging into a good debug.

Must-have skills and experience:

• Strong command of UVM methodology, with solid prior experience on a complete verification environment

• Strong command of SystemVerilog for verification (classes, constraints, interfaces, SVA assertions), and the ability to read and understand RTL (Verilog / SystemVerilog / VHDL)

• Hands-on experience with functional coverage and code coverage techniques, and a good understanding of coverage closure (gap analysis, waivers)

• Experience verifying at least one standard communication protocol (APB/AHB/AXI, I2C/SPI/I3C, or equivalent)

• Good scripting skills (Tcl, Shell, Python, Perl...) for automating verification flows and regressions

• Comfortable working in both Linux and Windows environments

• Hands-on experience with EDA simulation, coverage, and debug tools (Cadence, Siemens EDA, Synopsys)

Preferred skills and experience:

• Some exposure to ISO 26262 functional safety verification and fault injection campaigns

• Prior experience in formal verification (Questa Formal, JasperGold, or equivalent)

• Familiarity with SVN and