Digital IC Verification Engineer

PROPHESEE; Paris; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

A technology innovator in neuromorphic vision systems is seeking a Digital IC/ASIC Verification Engineer in Paris. The ideal candidate will have over 8 years of experience in digital IC design verification and will be accountable for developing tests and verifying complex digital circuits. You will work closely with the R&D team, defining methodologies, running simulations, and preparing detailed reports. Applicants should hold an MSc or PhD and possess strong skills in C++ and System Verilog. Fluent English is mandatory.

Qualifications

• 8+ years of hands-on experience in Digital IC design verification.
• Fluent oral and written communication in English.

Responsabilités

• Define and implement verification methodologies.
• Prepare detailed specifications, verification plan, test protocols, and reports.
• Run simulations and implement regression tests.
• Contribute to support activities for technical post-sales issues.

Connaissances

C++

System C

Python

Shell scripting

Linux utilization

System Verilog

UVM methodology

Verilog/VHDL

SVA

PSL

Cadence IES

Mentor Graphics Questa

Git

SVN

Continuous Development

Continuous Integration

Formation

MSc or PhD in Electrical Engineering, Computer Engineering, Physics

Description du poste

About PROPHESEE

Prophesee is the inventor of the world’s most advanced neuromorphic vision systems. The company developed a breakthrough event-based vision approach to machine vision that enables dramatic reductions in power consumption, latency, and data processing requirements. By mimicking how the human eye and brain work, Prophesee’s patented Metavision® sensors and algorithms reveal information that is invisible to traditional frame-based sensors. Prophesee’s technology is transforming applications across industrial automation, aerospace and defense, autonomous systems, IoT, AR/VR, and mobile. Headquartered in Paris, Prophesee has offices in Grenoble and Shanghai.

Job background

We are looking for a passionate individual who demonstrates initiative, takes ownership, respects commitments, and exhibits a high level of autonomy and spirit of innovation. The ideal candidate would be a multitasking and creative digital IC/ASIC verification engineer. You will be accountable for developing tests and for verifying complex digital circuits to be integrated in the digital part of the neuromorphic vision sensor. Moreover, you will be defining coverage points and metrics. You will have the responsibility of building block and top level random constrained test benches, creating directive tests for verification and coverage closure, running simulations, regressions and debugging failures working closely with design engineers. The day-to-day working environment is a small but impacting Digital Front End IC team (~7-10 people). You will be in contact with plenty of other engineering fields (Analog IC team, Systems Team, Software Algorithm team, etc..) and will also participate in silicon bring-up in laboratory when back from foundry.

Job details

• Define and implement verification methodologies.
• Define block and top-level random constrained test benches.
• Run simulations (on RTL and netlist).
• Implement regression tests.
• Define signoff methodologies.
• Support analog team in setting up mixed-mode simulations.
• Prepare detailed written specifications, verification plan, test protocols and test reports.
• Coverage: Setup flow, evaluate, report, enhance, signoff.
• Work in close collaboration with the whole R&D team.
• Contribute to the support activities for any technical post-sales issues.
• Keep up to date with new standards and general market information in the Industry.
• Participate in Technology / Supplier / Tool Selection.
• Participate in developing methodologies and flow efficiencies.

Travel Requirements

• Up to 10% of the working time.

Required Qualifications, Experience, And Skills

Education

MSc or PhD in Electrical Engineering, Computer Engineering, Physics, or similar

Experience

8+ years of hands-on experience in Digital IC design verification.

Required Skills And Experience

• C++, System C, Python, shell scripting, Linux utilization
• System Verilog and UVM methodology
• Hardware description languages (Verilog/VHDL) and RTL design flow
• SVA and/or PSL
• Experience in simulation and debugging tools such as Cadence IES or Mentor Graphics Questa
• Experience in functional and code coverage
• Experience with versioning tools (Git, SVN, ...)
• Experience in task estimation and planning awareness
• Experience with Continuous Development (CD) and Continuous Integration (CI) flow and tools

Preferred Skills

• FPGAs/ASICs design
• Experience in image/vision sensor processing, USB, I2C, MIPI protocols
• Experience in DFT verification
• Experience in formal verification
• Experience in gate level simulation (GLS)
• Experience with Firmware verification, development

Language skill

Fluent oral and written communication in English is mandatory.

Personal Skills

Strong problem-solving skills, strong analytical skills. Flexible to dynamic environments and fast changing technologies. Passionate about technology. This person must work well with other engineers in a team environment. Good sense of autonomy. Must be pragmatic and self-motivated to complete a task even if it is outside of just the “well known” realm. “Can Do Attitude” is preferred.