Senior IP Verification Engineer – Power Management & Safety

Dolphin Design SAS; Meylan; Sur place; EUR 70 000 - 100 000; Plein temps

Résumé du poste

Dolphin Design SAS, based in Meylan, France, is seeking an IP Verification Engineer to join the verification team. The role focuses on functional verification of power management IPs and involves UVM testbenches, protocol checks, and coverage strategies.

You will contribute to ISO 26262 safety verification campaigns, fault injection, and formal verification while growing your expertise across UVM, SystemVerilog, and EDA tools in a dynamic hardware environment.

Qualifications

• Requires a strong UVM-based verification background.
• Solid SystemVerilog (classes, constraints, interfaces) and RTL understanding.
• Experience with functional/coverage-driven verification and SVA assertions is essential.
• Familiarity with ISO 26262 functional safety aspects is advantageous.

Responsabilités

• Develop and maintain verification plans from specifications.
• Build and debug UVM environments with agents, sequences, scoreboards.
• Create reusable, parameterized SystemVerilog testbenches across IPs.
• Write constrained-random stimuli and checks; develop protocol coverage.
• Support fault injection, safety verification, and formal verification activities.
• Collaborate with seniors, leads, and designers to drive verification closure.

Connaissances

UVM

SystemVerilog

SVA assertions

RTL

Code coverage

Scripting

Linux/Windows

EDA tools

Formation

Engineering degree or Master's degree (Bac+5)

Outils

Cadence

Siemens EDA

Synopsys

Questa Formal

JasperGold

Description du poste

Dolphin Design SAS, based in Meylan, France, is seeking an IP Verification Engineer to join the verification team. The role focuses on functional verification of power management IPs and involves UVM testbenches, protocol checks, and coverage strategies.

You will contribute to ISO 26262 safety verification campaigns, fault injection, and formal verification while growing your expertise across UVM, SystemVerilog, and EDA tools in a dynamic hardware environment.