Senior RISC-V Verification Engineer (France)

Codasip; Nice; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

Codasip is seeking Verification Engineers to help bring our vision to life. You’ll verify complex, state‑of‑the‑art CPUs, including advanced out‑of‑order processors, taking ownership of portions of the design and applying a range of verification methodologies.

Based at our design center in Villeneuve-Loubet, near Sophia Antipolis, you’ll collaborate with an international team spanning Europe to set high verification standards for a brand‑new platform and contribute to high‑quality,

Qualifications

• Commercial experience with functional processor verification methodologies.
• Knowledge of verifying CPU architectures or other IP.
• Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go.
• Past verification ownership of a design block.
• User knowledge of Linux to enable automation of common tasks.
• Knowledge of versioning tools (Git, SVN).
• Knowledge of RISC-V Architecture.
• Good knowledge of computer systems and architecture.
• Analytical thinking and team collaboration skills.
• Ability to work effectively across teams to debug issues and find root causes.

Responsabilités

• Verify RISC-V processors and extensions
• Develop verification solutions (e.g., test benches and test bench components, stimulus generation, formal environments)
• Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
• Define verification strategies for blocks and sub-systems, identifying and utilising the right tools
• Review technical specifications, providing feedback from a verification perspective
• Run simulations, hunt bugs and complete root cause analysis of complex issues
• Define, estimate, prioritise and track your own work
• Track and report verification metrics
• Craft automated verification flows

Connaissances

SystemVerilog

Python

C++

Rust

Go

Linux

Git

RISC-V

Verification ownership

Team collaboration

Description du poste

Codasip is seeking Verification Engineers to help bring our vision to life. You’ll verify complex, state‑of‑the‑art CPUs, including advanced out‑of‑order processors, taking ownership of portions of the design and applying a range of verification methodologies.

Based at our design center in Villeneuve-Loubet, near Sophia Antipolis, you’ll collaborate with an international team spanning Europe to set high verification standards for a brand‑new platform and contribute to high‑quality,