Senior Digital Verification Engineer — SystemVerilog/UVM Expert

NXP Semiconductors NV; Grenoble; On-site; EUR 70,000 - 100,000; Full time

Job summary

NXP Semiconductors Netherlands B.V. is seeking a highly skilled Senior HW Digital Design Verification Engineer to join our team. You will define and implement verification strategies for complex digital designs, ensuring robustness and correctness of semiconductor products.

Responsibilities include developing plans, building testbenches, and applying UVM/formal methods. Collaborate across design, architecture, and software teams while mentoring junior engineers.

Qualifications

• Bachelor's or master's in Electrical/Computer Engineering or related field.
• 5+ years of digital design verification of complex ASICs/SoCs.
• Strong SystemVerilog and UVM knowledge; test plan development.
• Experience with verification tools and scripting languages.

Responsibilities

• Develop verification plans for complex digital blocks and sub-systems, including testbench architecture and coverage closure.
• Implement UVM and formal verification techniques.
• Create and maintain verification environments using SystemVerilog, UVM, OVM, and e.
• Develop directed, constrained-random, and assertion-based testbenches to validate design functionality.
• Perform functional and code coverage analysis to ensure verification completeness.
• Debug design/verification issues and collaborate with design teams to identify root causes.
• Collaborate with design, architecture and software teams on requirements and specs.
• Contribute to continuous improvement of verification methodologies, flows and tools.
• Mentor junior engineers and share technical expertise.

Skills

SystemVerilog

UVM

Python

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

OVM

e

Waveform viewers

Job description

NXP Semiconductors Netherlands B.V. is seeking a highly skilled Senior HW Digital Design Verification Engineer to join our team. You will define and implement verification strategies for complex digital designs, ensuring robustness and correctness of semiconductor products.

Responsibilities include developing plans, building testbenches, and applying UVM/formal methods. Collaborate across design, architecture, and software teams while mentoring junior engineers.